Public Version
www.ti.com
Display Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
Indicates that the video port works but the configuration of the
timings for the display controller (DISPC) and for DSI protocol
engine may have to be modified to avoid the resynchronization
to occur.
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is
reset.
4
WAKEUP_IRQ
Wakeup
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
3
VIRTUAL_CHANNEL3_
Virtual channel #3
R
0x0
IRQ
Error signaling from DSI Virtual Channel3: Status of DSI Virtual
Channel3 errors received from DSI Virtual Channel3 (events are
defined in DSI_VC3_IRQSTATUS).
0x0: READS: Event is false.
0x1: READS: Event is true (pending).
2
VIRTUAL_CHANNEL2_
Virtual channel #2
R
0x0
IRQ
Error signaling from DSI Virtual Channel2: Status of DSI Virtual
Channel2 errors received from DSI Virtual Channel2 (events are
defined in DSI_VC2_IRQSTATUS).
0x0: READS: Event is false.
0x1: READS: Event is true (pending).
1
VIRTUAL_CHANNEL1_
Virtual channel #1
R
0x0
IRQ
Error signaling from DSI Virtual Channel1: Status of DSI Virtual
Channel1 errors received from DSI Virtual Channel1 (events are
defined in DSI_VC1_IRQSTATUS).
0x0: READS: Event is false.
0x1: READS: Event is true (pending).
0
VIRTUAL_CHANNEL0_
Virtual channel #0
R
0x0
IRQ
Error signaling from DSI Virtual Channel0: Status of the DSI
Virtual Channel0 errors received from DSI Virtual Channel0
(events are defined in DSI_VC0_IRQSTATUS).
0x0: READS: Event is false.
0x1: READS: Event is true (pending).
Table 7-375. Register Call Summary for Register DSI_IRQSTATUS
Display Subsystem Integration
•
:
Display Subsystem Functional Description
•
:
•
•
:
•
•
:
Display Subsystem Basic Programming Model
•
:
•
•
•
:
Display Subsystem Use Cases and Tips
•
:
•
:
1913
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated