OUT_P
0.1µF
C25
0.1µF
C24
0
R25
0
R28
LAYOUT NOTE:
Place shunt resistors
near the output pins.
OUT_N
R_OUT_P
R_OUT_N
LAYOUT NOTE:
Place close to SMA
ports.
LAYOUT NOTE:
Individual vias to
GND on shunt
resistors.
OE
1
ADD
2
GND
3
SCL
8
OUTP
4
OUTN
5
VCC
6
SDA
7
U5
LMK06001SIA
GND
SDA
SCL
VDD
OE
ADD
1
2
3
4
5
P2
OUTP
1
2
3
4
5
P3
OUTN
SH5_2_3
1
2
3
J9
FS0
4.7k
R21
VDD
4.7k
R23
GND
SH6_2_3
1
2
3
J10
FS1
4.7k
R22
VDD
4.7k
R24
GND
0.01µF
C22
GND
LABEL PINS:
1 = VDD
2 = <JP NAME>
3 = GND
LABEL PINS:
1 = VDD
2 = <JP NAME>
3 = GND
LMK61XX
4.7µF
C23
GND
0
R27
DNP
100
R31
0
R30
DNP
150
R26
150
R29
EVM Schematic
20
LMK61E2EVM User's Guide
SNAU188 – October 2015
Copyright © 2015, Texas Instruments Incorporated