(
)
DRATE _ E
DATA
XOSC
28
256 DRATE _ M
2
R
f
2
+
´
=
´
SWRS037B – JANUARY 2006 – REVISED MARCH 2015
5.6.2
General Control and Status Pins
The CC1150 has one dedicated configurable pin (GDO0) and one shared pin (GDO1/SO) that can output
internal status information useful for control software. These pins can be used to generate interrupts on
the MCU. See
for more details of the signals that can be programmed. The shared pin is the
SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of
the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will
always function as a normal SO pin.
In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin
while in transmit mode.
The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on
the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature
sensor are found in
. With default PTEST register setting (0x7F), the temperature sensor
output is only available when the frequency synthesizer is enabled (for example, the MANCAL, FSTXON
and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor
in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value
(0x7F).
5.6.3
Optional Radio Control Feature
The CC1150 has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI
interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE,
and TX.
This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit.
State changes are commanded as follows:
•
If CSn is high, the SI and SCLK are set to the desired state according to
.
•
If CSn goes low, the state of SI and SCLK is latched and a command strobe is generated internally
according to the pin configuration.
It is only possible to change state with the latter functionality. That means that for instance TX will not be
restarted if SI and SCLK are set to TX and CSn toggles. When CSn is low the SI and SCLK has normal
SPI functionality.
All pin control command strobes are executed immediately except the SPWD strobe. The SPWD strobe is
delayed until CSn goes high.
Table 5-3. Optional Pin Control Coding
CSn
SCLK
SI
FUNCTION
1
X
X
Chip unaffected by SCLK/SI
↓
0
0
Generates SPWD strobe
↓
0
1
Generates STX strobe
↓
1
0
Generates SIDLE strobe
↓
1
1
Defined on the transceiver version (CC1101)
SPI mode (wakes up into IDLE if in
0
SPI mode
SPI mode
SLEEP/XOFF)
5.7
Data Rate Programming
The data rate used when transmitting is programmed by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As
shows, the programmed data rate depends on the crystal frequency.
(1)
18
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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