Texas Instruments CC1150, Manual

Page: 38 / 66

BALUN,
Matching and
Filtering
Antenna
PA
Filter
CC1150
CC1150
SWRS037B – JANUARY 2006 – REVISED MARCH 2015 www.ti.com
5.19.6 Low-Cost Systems
As the CC1150 provides 500-kBaud multi-channel performance without any external filters, a very low cost
system can be made. A HC-49 type SMD crystal is used in the CC1150EM reference design (see
[1] and
[2] ).
NOTE
The crystal package strongly influences the price. In a size constrained PCB design a
smaller, but more expensive, crystal may be used.
5.19.7 Battery-Operated Systems
In low power applications, the SLEEP state should be used when the CC1150 is not active.
5.19.8 Increasing Output Power
In some applications it may be necessary to extend the link range. Adding an external power amplifier is
the most effective way of doing this.
The power amplifier should be inserted between the antenna and the balun as shown in Figure 5-18 .
Figure 5-18. Block Diagram of CC1150 Usage with External Power Amplifier
5.20 Memory
The configuration of CC1150 is done by programming 8-bit registers. The configuration data based on
selected system parameters are most easily found by using the SmartRF Studio
[11] software. Complete
descriptions of the registers are given in Section 5.20.1 . After chip reset, all the registers have default
values as shown in the tables. The optimum register setting might differ from the default value. After a
reset, all registers that shall be different from the default value therefore needs to be programmed through
the SPI interface.
There are 9 Command Strobe Registers, listed in Table 5-11 Accessing these registers will initiate the
change of an internal state or mode. There are 29 normal 8-bit Configuration Registers, listed in Table 5-
12 . Many of these registers are for test purposes only, and need not be written for normal operation of
CC1150.
There are also 6 Status registers, which are listed in Table 5-13 . These registers, which are read-only,
contain information about the status of CC1150.
The TX FIFO is accessed through one 8-bit register. Only write operations are allowed to the TX FIFO.
During the address transfer and while writing to a register or the TX FIFO, a status byte is returned. This
status byte is described in
Table 5-2 .
38 Detailed Description
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