Texas Instruments CC1150, Manual

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0 A6 A5 A4 A3 A2 A0 A1 D
W
7 D
W
6 D
W
5 D
W
4 D
W
3 D
W
2 D
W
1 D
W
0
1
A6 A5 A4 A3 A2 A0 A1
D
R
7 D
R
6 D
R
5 D
R
4 D
R
3 D
R
2 D
R
1 D
R
0
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO
Hi-Z
t
sp
t
ch
t
cl
t
sd
t
hd
t
ns
X X
Hi-Z
X
S7 S6 S5 S4 S3 S2 S1 S0
Hi-Z
S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7
X
CC1150
SWRS037B – JANUARY 2006 – REVISED MARCH 2015 www.ti.com
Figure 5-4. Configuration Registers Write and Read Operations
Table 5-1. SPI Interface Timing Requirements
PARAMETER DESCRIPTION MIN MAX UNIT
SCLK frequency
— 10
100 ns delay inserted between address byte and data byte (single access), or
between address and data, and between each data byte (burst access).
SCLK frequency, single access
f
SCLK
MHz
9
No delay between address and data byte
SCLK frequency, burst access
6.5
No delay between address and data byte, or between data bytes
t
sp,pd
CSn low to positive edge on SCLK, in power-down mode 150 — µs
t
sp
CSn low to positive edge on SCLK, in active mode 20 — ns
t
ch
Clock high 50 — ns
t
cl
Clock low 50 — ns
t
rise
Clock rise time — 5 ns
t
fall
Clock fall time — 5 ns
Setup data (negative SCLK edge) to positive edge on Single access
55 — ns
SCLK
t
sd
(t
sd
applies between address and data bytes, and Burst access
76 — ns
between data bytes)
t
hd
Hold data after positive edge on SCLK 20 — ns
t
ns
Negative edge on SCLK to CSn high 20 — ns
NOTE
The minimum t
sp,pd
figure in Table 5-1 can be used in cases where the user does not read
the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from
power-down depends on the start-up time of the crystal being used. The 150
μ
s in Table 5-1
is the crystal oscillator start-up time measured using crystal AT-41CD2 from NDK.
5.5.1 Chip Status Byte
When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is
sent by the CC1150 on the SO pin. The status byte contains key status signals, useful for the MCU. The
first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.
Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power
to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and
channel configuration should only be updated when the chip is in this state. The TX state will be active
when the chip is transmitting.
14 Detailed Description
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