Texas Instruments CC1150, Manual

Page: 16 / 66

CSn
SO
SI
SRES
Sxxx Sxxx
CC1150
SWRS037B – JANUARY 2006 – REVISED MARCH 2015 www.ti.com
NOTE
An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This
means that if for example an SIDLE strobe is issued while the radio is in TX state, any other
command strobes issued before the radio reaches IDLE state will be ignored.
The command strobe registers are accessed in the same way as for a register write operation, but no data
is transferred. That is, only the R/W bit (set to 0), burst access (set to 0) and the six address bits (in the
range 0x30 through 0x3D) are written.
When writing command strobes, the status byte is sent on the SO pin.
A command strobe may be followed by any other SPI access without pulling CSn high. However, if an
SRES command strobe is being issued, on will have to wait for the SO pin to go low before the next
command strobe can be issued as shown in
Figure 5-5 .The command strobes are executed immediately,
with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.
Figure 5-5. SRES Command Strobe
5.5.5 FIFO Access
The 64-byte TX FIFO is accessed through the 0x3F addresses. When the read/write bit is zero, the TX
FIFO is accessed. The TX FIFO is write-only.
The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access
method expects address with burst bit set to zero and one data byte. After the data byte a new address is
expected; hence, CSn can remain low. The burst access method expects one address byte and then
consecutive data bytes until terminating the access by setting CSn high.
The following header bytes access the FIFO:
• 0x3F: Single byte access to TX FIFO
• 0x7F: Burst access to TX FIFO
When writing to the TX FIFO, the status byte (see Section 5.5.1 ) is output for each new data byte on SO,
as shown in Figure 5-5 . This status byte can be used to detect TX FIFO underflow while writing data to
the TX FIFO.
NOTE
The status byte contains the number of bytes free before writing the byte in progress to the
TX FIFO.
When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received
concurrently on the SO pin will indicate that one byte is free in the TX FIFO.
The TX FIFO may be flushed by issuing a SFTX command strobe. The SFTX command strobe can only
be issues in the IDLE or TX_UNDERFLOW states. The FIFO is cleared when going to the SLEEP state.
Figure 5-6 gives a brief overview of different register access types possible.
16 Detailed Description
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