Texas Instruments CC1150, Manual

Page: 17 / 66

DATA
byte 0
ADDR
FIFO
DATA
byte 1
DATA
byte 2
DATA
byte n-1
DATA
byte n
...
ADDR
strobe
DATA
ADDR
strobe
ADDR
reg
ADDR
reg n
DATA
n
DATA
n+1
DATA
n+2
...
ADDR
strobe
...
CSn:
Command strobe(s):
Read or write register(s):
Read or write consecutive registers (burst):
DATA ADDR
reg
DATA ADDR
reg
...
DATA
byte 0
ADDR
FIFO
DATA
byte 1
Combinations: DATA ADDR
reg
DATA ADDR
reg
ADDR
strobe
ADDR
strobe
...
Read or write n+1 bytes from/to RF FIFO:
CC1150
www.ti.com SWRS037B – JANUARY 2006 – REVISED MARCH 2015
Figure 5-6. Register Access Types
5.5.6 PATABLE Access
The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings.
The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE,
controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for
reduced bandwidth.
NOTE
The ASK modulation shaping is limited to output powers below –1 dBm. See SmartRF Studio
[11] for recommended shaping sequence.
See also Section 5.16 for details on output-power programming.
The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power
values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest
setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the
table. This counter is incremented each time a byte is read or written to the table, and set to the lowest
index when CSn is high. When the highest value is reached the counter restarts at zero.
The access to the PATABLE is either single byte or burst access depending on the burst bit. When using
burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write
bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).
If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before
the read access in order to set the index counter back to zero.
NOTE
The content of the PATABLE is lost when entering the SLEEP state. For more information,
see
DN501 [8] .
5.6 Microcontroller Interface and Pin Configuration
In a typical system, CC1150 will interface to a microcontroller. This microcontroller must be able to do the
following:
• Program CC1150 into different modes
• Write buffered data
• Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn)
5.6.1 Configuration Interface
The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The
SPI is described in
Section 5.5 .
Copyright © 2006–2015, Texas Instruments Incorporated
Detailed Description 17
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