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Fast Interrupt Response

Fast Interrupt Response

The fast interrupt response, with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. C28x implements a
zero cycle penalty to do 14 registers context saved and restored during an interrupt. This feature
helps reduces the interrupt service routine overheads.

C28x Fast Interrupt Response Manager

C28x Fast Interrupt Response Manager

¾

¾

96 dedicated PIE

96 dedicated PIE

vectors

vectors

¾

¾

No software decision

No software decision

making required

making required

¾

¾

Direct access to RAM

Direct access to RAM

vectors

vectors

¾

¾

Auto flags update

Auto flags update

¾

¾

Concurrent auto

Concurrent auto

context save

context save

28x CPU Interrupt logic

28x CPU Interrupt logic

28x

28x

CPU

CPU

INTM

INTM

IFR

IFR

IER

IER

96

96

P

e

ri

ph

er

al

In

te

rr

u

p

ts

1

2

x8 = 96

P

e

ri

ph

er

al

In

te

rr

u

p

ts

1

2

x8

=

96

12 interrupts

12 interrupts

INT1 to

INT1 to

INT12

INT12

PIE

PIE

Register

Register

Map

Map

PIE module

PIE module

For 96

For 96

interrupts

interrupts

T

T

ST0

ST0

AH

AH

AL

AL

PH

PH

PL

PL

AR1 (L)

AR1 (L)

AR0 (L)

AR0 (L)

DP

DP

ST1

ST1

DBSTAT

DBSTAT

IER

IER

PC(msw)

PC(msw)

PC(lsw)

PC(lsw)

Auto Context Save

Auto Context Save

C28x - Architecture Overview

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Summary of Contents for C28 Series

Page 1: ...TI C28x DSP Design Workshop Student Guide Technical Training Organization C28x Revision 5 0 February 2004 ...

Page 2: ...s using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right c...

Page 3: ...cal Training Organization Organization T TTO TO eZdsp F2812 Starter Kit eZdsp eZdsp is a trademark of Spectrum Digital Inc is a trademark of Spectrum Digital Inc Introductions Introductions Introductions Name Name Company Company Project Responsibilities Project Responsibilities DSP Microcontroller Experience DSP Microcontroller Experience TMS320 DSP Experience TMS320 DSP Experience Hardware Softw...

Page 4: ...ager Event Manager 8 8 Numerical Concepts and IQ Math Numerical Concepts and IQ Math 9 9 Using DSP BIOS Using DSP BIOS 10 10 System Design System Design 11 11 Communications Communications 12 12 Support Resources Support Resources eZdsp F2812 Hardware eZdsp eZdsp F2812 Hardware F2812 Hardware Parallel Port Parallel Port JTAG JTAG Controller Controller Interface P3 Interface P3 I O Interface P4 P8 ...

Page 5: ...ning Objectives When this module is complete you should have a basic understanding of the C28x architecture and how all of its components work together to create a high end uniprocessor control system Learning Objectives Learning Objectives Identify the three main components Identify the three main components of the C28x of the C28x List the key features of the C28x List the key features of the C2...

Page 6: ... 3 C28x CPU 1 4 Multiplier ALU and Shifters 1 5 TMS320C28x Internal Bussing 1 6 Special Instructions 1 7 Pipeline Advantage 1 8 Memory 1 9 Memory Map 1 9 Code Security Module CSM 1 10 Peripherals 1 10 Fast Interrupt Response 1 11 C28 Mode 1 12 Reset 1 13 Summary 1 14 1 2 C28x Architecture Overview ...

Page 7: ...ata Bus RAM RAM RAM Boot ROM Boot Boot ROM ROM 22 22 32 bit Auxiliary Registers 32 32 bit bit Auxiliary Auxiliary Registers Registers 3 32 bit Timers 3 3 32 bit 32 bit Timers Timers Realtime JTAG Realtime Realtime JTAG JTAG CPU CPU Register Bus Register Bus R M W Atomic ALU R R M M W W Atomic Atomic ALU ALU PIE PIE Interrupt Interrupt Manager Manager 32 32 32 32 32 32 Event Manager A Event Event M...

Page 8: ... Timers Realtime JTAG Realtime Realtime JTAG JTAG CPU CPU Register Bus Register Bus R M W Atomic ALU R R M M W W Atomic Atomic ALU ALU Program Bus Program Bus MCU DSP balancing code density MCU DSP balancing code density execution time execution time Supports 32 Supports 32 bit instructions bit instructions for improved execution time for improved execution time Supports 16 Supports 16 bit instruc...

Page 9: ...Shift R L 0 16 16 32 32 16 16 The 32 x 32 bit MAC capabilities of the C28x and its 64 bit processing capabilities enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating point processor solution Along with this is the capability to perform two 16 x 16 bit multiply accumulate instructions simultaneously or Dual MACs DMAC C28x ...

Page 10: ...s 32 JTAG JTAG Program Program Decoder Decoder PC PC XAR0 XAR0 to to XAR7 XAR7 SP SP DP DP X X ARAU ARAU MPY32x32 MPY32x32 XT XT P P ACC ACC ALU ALU Registers Registers Debug Debug Register Bus Result Bus Register Bus Result Bus Data Program Data Program write Data Bus 32 write Data Bus 32 Data Data read Address Bus 32 read Address Bus 32 Data Data read Data Bus 32 read Data Bus 32 Memory Memory D...

Page 11: ...nt compiler More efficient compiler AND XAR2 1234h AND XAR2 1234h 2 words 1 cycles 2 words 1 cycles Atomic Read Modify Write Atomic Read Modify Write MOV MOV AL XAR2 AL XAR2 AND AND AL 1234h AL 1234h MOV MOV XAR2 AL XAR2 AL DINT DINT EINT EINT 6 words 6 cycles 6 words 6 cycles Standard Load Store Standard Load Store Atomics are small common instructions that are non interuptable The atomic ALU cap...

Page 12: ...W W E G Access E G Access same address same address R R1 1 R R2 2 X X W W D D2 2 R R1 1 R R2 2 X W X W F1 Instruction Address F1 Instruction Address F2 Instruction Content F2 Instruction Content D1 Decode Instruction D1 Decode Instruction D2 Resolve Operand Addr D2 Resolve Operand Addr R1 Operand Address R1 Operand Address R2 Get Operand R2 Get Operand X CPU doing real work X CPU doing real work W...

Page 13: ...ARAM 4K L1 SARAM 4K L1 SARAM 4K HO SARAM 8K HO SARAM 8K Boot ROM 4K Boot ROM 4K MP MC 0 MP MC 0 BROM vector 32 BROM vector 32 MP MC 0 ENPIE 0 MP MC 0 ENPIE 0 OTP 1K OTP 1K FLASH 128K FLASH 128K reserved reserved reserved PF 0 2K PF 0 2K reserved reserved PF 1 4K PF 1 4K reserved PF 2 4K PF 2 4K reserved PIE vector PIE vector 256 256 ENPIE 1 ENPIE 1 XINT Zone 0 8K XINT Zone 1 8K XINT Zone 2 0 5M XI...

Page 14: ... at 150 MHz it would take at least 1 4 x 10 would take at least 1 4 x 1023 23 years to try all years to try all possible combinations possible combinations LO SARAM 4K LO SARAM 4K L1 SARAM 4K L1 SARAM 4K OTP 1K OTP 1K FLASH 128K FLASH 128K reserved 0x00 8000 0x00 8000 0x00 9000 0x00 9000 0x00 A000 0x00 A000 0x3D 7800 0x3D 7800 0x3D 8000 0x3D 8000 128 128 Bit Password Bit Password reserved 0x3D 7C0...

Page 15: ...o software decision No software decision making required making required Direct access to RAM Direct access to RAM vectors vectors Auto flags update Auto flags update Concurrent auto Concurrent auto context save context save 28x CPU Interrupt logic 28x CPU Interrupt logic 28x 28x CPU CPU INTM INTM IFR IFR IER IER 96 96 Peripheral Interrupts 12x8 96 Peripheral Interrupts 12x8 96 12 interrupts 12 in...

Page 16: ...x Mode 1 1 0 0 Test Mode default Test Mode default 0 0 0 0 Reserved Reserved 0 0 1 1 OBJMODE AMODE OBJMODE AMODE Mode Bits Mode Bits Compiler Compiler Option Option Mode Type Mode Type C24x source C24x source compatible mode compatible mode Allows you to run C24x source code which has been reassembled Allows you to run C24x source code which has been reassembled using the C28x code generation tool...

Page 17: ...boot ROM from boot ROM 0x3F FFC0 0x3F FFC0 XMPNMC 0 XMPNMC 0 microcomputer mode microcomputer mode Execution Execution Entry Point Entry Point H0 SARAM H0 SARAM Note Note Details of the various boot options will be Details of the various boot options will be discussed in the Reset and Interrupts module discussed in the Reset and Interrupts module Bootloader Bootloader sets sets OBJMODE 1 OBJMODE 1...

Page 18: ...write instructions 8 8 stage fully protected pipeline stage fully protected pipeline Fast interrupt response manager Fast interrupt response manager 128Kw on 128Kw on chip flash memory chip flash memory Code security module CSM Code security module CSM Two event managers Two event managers 12 12 bit ADC module bit ADC module 56 shared GPIO pins 56 shared GPIO pins Watchdog timer Watchdog timer Com...

Page 19: ...Learning Objectives Use Code Composer Studio to Use Code Composer Studio to Create a Create a Project Project Set Set Build Options Build Options Create a Create a user user linker command file which linker command file which Describes a system s available memory Describes a system s available memory Indicates where sections will be placed Indicates where sections will be placed in memory in memor...

Page 20: ...2 5 Build Options 2 6 Creating a Linker Command File 2 9 Sections 2 9 Linker Command Files cmd 2 12 Memory Map Description 2 12 Section Placement 2 14 Exercise 2a 2 15 Summary Linker Command File 2 16 Lab 2a Linker Command File 2 17 DSP BIOS Configuration Tool 2 21 Lab 2b DSP BIOS Configuration Tool 2 26 Solutions 2 30 2 2 C28x Programming Development Environment ...

Page 21: ...ling Profiling SIM SIM eZdsp eZdsp EVM EVM Third Third Party Party XDS XDS DSP DSP Board Board DSP BIOS DSP BIOS Config Config Tool Tool DSP BIOS DSP BIOS Libraries Libraries lnk lnk cmd cmd Build Build Code Composer Studio includes a built in editor compiler assembler linker and an automatic build process Additionally tools to connect file input and output as well as built in graph displays for o...

Page 22: ...benefits of modularity by allowing the programmer to focus on the code and not waste time managing memory and moving code as other code components grow or shrink A linker is invoked to allocate systems hardware to the modules desired to build a system Changes in any or all modules when re linked create a new hardware allocation avoiding the possibility of memory resource conflicts Code Composer St...

Page 23: ... configuration Linker command files Linker command files Project settings Project settings Build Options compiler and Build Options compiler and assembler assembler Build configurations Build configurations DSP BIOS DSP BIOS Linker Linker Project Project pjt pjt files contain files contain The project information is stored in a PJT file which is created and maintained by CCS To create a new projec...

Page 24: ...uration options Build Options GUI Build Options GUI Compiler Compiler GUI has 8 pages of categories for code GUI has 8 pages of categories for code generation tools generation tools Controls many aspects of the build process Controls many aspects of the build process such as such as Optimization level Optimization level Target device Target device Compiler assembly link options Compiler assembly l...

Page 25: ...t pjt location location There are many linker options but these four handle all of the basic needs o filename specifies the output executable filename m filename creates a map file This file reports the linker s results c tells the compiler to autoinitialize your global and static variables x tells the compiler to exhaustively read the libraries Without this option libraries are searched only once...

Page 26: ...CS automatically creates two build configurations creates two build configurations Debug Debug unoptimized unoptimized Release Release optimized optimized Use the drop Use the drop down menu to quickly down menu to quickly select the build configuration select the build configuration To help make sense of the many compiler options TI provides two default sets of options configurations in each new ...

Page 27: ...itialized uninitialized sections sections int int x 2 x 2 int int y 7 y 7 void main void void main void long z long z z x y z x y Global Vars ebss ebss Init vals cinit cinit Local vars stack stack Code text text In the TI code generation tools as with any toolset based on the COFF Common Object File Format these various parts of a program are called Sections Breaking the program code and data into...

Page 28: ...ng the separate sections for code constants and variables In this way they can all be linked located into their proper memory locations in your target embedded system Generally they re located as follows Program Code text Program code consists of the sequence of instructions used to manipulate data initialize system settings etc Program code must be defined upon system reset power turn on Due to t...

Page 29: ...8000 0x3D 8000 0x00 0400 0x00 0400 M1SARAM M1SARAM 0x400 0x400 FLASH FLASH 0x20000 0x20000 Sections Sections stack stack Linking code is a three step process 1 Defining the various regions of memory on chip SARAM vs FLASH vs External Memory 2 Describing what sections go into which memory regions 3 Running the linker with build or rebuild C28x Programming Development Environment 2 11 ...

Page 30: ...o place s w into h w Memory Map Description Describe the memory configuration of your target system to the linker Without this specification the linker might place code or data into memory that doesn t exist The format is Name origin 0x length 0x For example if you placed a 2K EPROM starting at memory location zero it would read MEMORY EPROM origin 0x0000 length 0x0800 You define each memory segme...

Page 31: ...these Linker Page TI Definition Page 0 Program Page 1 Data Linker Command File Linker Command File MEMORY MEMORY PAGE 0 Program Space PAGE 0 Program Space FLASH org 0x3D8000 FLASH org 0x3D8000 len len 0x20000 0x20000 PAGE 1 Data Space PAGE 1 Data Space M0SARAM org 0x000000 M0SARAM org 0x000000 len len 0x400 0x400 M1SARAM org 0x000400 M1SARAM org 0x000400 len len 0x400 0x400 C28x Programming Develo...

Page 32: ...ions Beginning with the first section listed the linker will place it into the specified memory segment Linker Command File Linker Command File MEMORY MEMORY PAGE 0 PAGE 0 Program Space Program Space FLASH org 0x3D8000 FLASH org 0x3D8000 len len 0x20000 0x20000 PAGE 1 PAGE 1 Data Space Data Space M0SARAM org 0x000000 M0SARAM org 0x000000 len len 0x400 0x400 M1SARAM org 0x000400 M1SARAM org 0x00040...

Page 33: ...g in the blanks on the following slide Fill in the blanks Exercise 2a Exercise 2a Command File Command File Memory Memory PAGE__ Program Space PAGE__ Program Space _____ org ____ _____ org ____ ___ ___ len len ___ ___ ___ ___ ______ Data Space ______ Data Space _______ org ___ _______ org ___ ____ ____ len len _____ _____ _______ _______ org ____ org ____ ___ ___ len len _____ _____ _______ ______...

Page 34: ...Memory Map Description Memory Map Description Name Name Location Location Size Size Sections Description Sections Description Directs software sections into named Directs software sections into named memory regions memory regions Allows per Allows per file discrimination file discrimination Allows separate load run locations Allows separate load run locations 2 16 C28x Programming Development Envi...

Page 35: ...2812 Memory Memory on chip memory on on chip chip memory memory 0x00 0000 0x00 0000 0x00 0400 0x00 0400 0x00 8000 0x00 8000 0x00 9000 0x00 9000 0x3F 8000 0x3F 8000 H0SARAM 0x2000 H0SARAM H0SARAM 0x2000 0x2000 M1SARAM 0x400 M1SARAM M1SARAM 0x400 0x400 L1SARAM 0x1000 L1SARAM L1SARAM 0x1000 0x1000 L0SARAM 0x1000 L0SARAM L0SARAM 0x1000 0x1000 M0SARAM 0x400 M0SARAM M0SARAM 0x400 0x400 System Descriptio...

Page 36: ...exercise 5 Next add the compiler run time support library to the project C ti c2000 cgtools lib rts2800_ml lib 6 In the project window on the left click the plus sign to the left of Project Now click on the plus sign next to Lab2 pjt Notice that the Lab2a cmd file is listed Click on Source to see the current source file list i e Lab2 c Project Build Options 7 There are numerous build options in th...

Page 37: ...heck for errors we have deliberately put an error in Lab2 c When you get an error scroll the build window at the bottom of the Code Composer Studio screen until you see the error message in red and simply double click the error message The editor will automatically open the source file containing the error and position the mouse cursor at the correct code line 17 Fix the error by adding a semicolo...

Page 38: ...nction currently being executed Note that local variables actually live on the stack You can also view local variables in a memory window by setting the address to SP after the code function has been entered 22 We can also add global variables to the watch window if desired Let s add the global variable z Click the Watch 1 tab at the bottom of the watch window In the empty box in the Name column t...

Page 39: ... support libraries interrupt vectors interrupt vectors system reset etc system reset etc The GUI graphical user interface simplifies system design by Automatically including the appropriate runtime support libraries Automatically handles interrupt vectors and system reset Handles system memory configuration builds CMD file When a CDB file is saved the Config Tool generates 5 additional files Filen...

Page 40: ...d you can place sections into it shown in the next step Memory Section Manager Memory Section Manager Mem Mem manager allows manager allows you to create you to create memory area and memory area and place sections place sections To create a new To create a new memory area memory area Right Right click on MEM click on MEM and select Insert and select Insert memory memory Fill in base length Fill i...

Page 41: ...regions you defined in step 1 Memory Section Manager Properties Memory Section Manager Properties To place a section To place a section into a memory area into a memory area Right Right click on MEM click on MEM and select and select Properties Properties Select the Select the appropriate tab e g appropriate tab e g Compiler Compiler Select the memory Select the memory for each section for each se...

Page 42: ...ferent files Notice one of them is the Notice one of them is the linker command file linker command file CMD file is generated from CMD file is generated from your MEM settings your MEM settings cfg h28 cfg h28 cfg h cfg h cfg cmd cfg cmd cfg s28 cfg s28 cfg_c c cfg_c c MEMORY FLASH org 0x3D8000 len 0x20000 H0SARAM org 0x3F8000 len 0x2000 SECTIONS text FLASH bss M0SARAM MEMORY FLASH org 0x3D8000 l...

Page 43: ...l Linker Command File Tool Linker Command File Do not modify Do not modify appcfg appcfg cmd cmd your changes will your changes will be overwritten during Build or Rebuild be overwritten during Build or Rebuild app cdb Linker Linker appcfg cmd myApp out Build obj files libraries lib map The linker can create two outputs the executable out file and a report which describes the results of linking ma...

Page 44: ...SARAM in data space PAGE 1 into RAM Block M1SARAM in data space PAGE 1 stack into RAM Block M0SARAM in data space PAGE 1 stack into RAM Block M0SARAM in data space PAGE 1 F2812 F2812 Memory Memory on chip memory on on chip chip memory memory 0x00 0000 0x00 0000 0x00 0400 0x00 0400 0x00 8000 0x00 8000 0x00 9000 0x00 9000 0x3F 8000 0x3F 8000 H0SARAM 0x2000 H0SARAM H0SARAM 0x2000 0x2000 M1SARAM 0x400...

Page 45: ...for this lab On the menu bar click File New DSP BIOS Configuration A dialog box appears The CDB files shown in the aforementioned dialog box are called seed CDB files CDB files are used to configure many objects specific to the processor Select the c28xx cdb template and click OK 6 Save the configuration file by selecting File Save As and name it Lab cdb in C C28x LABS LAB2 Close the configuration...

Page 46: ...s Click OK to save your work Set the Stack Size in the CDB File 13 Recall in the previous lab exercise that the stack size was set using the CCS project Build Options When using the DSP BIOS configuration tool the stack size is instead specified in the CDB file First we need to remove the stack size setting from the project Build Options 14 Click Project Build Options and select the Linker tab Del...

Page 47: ...uration Tool 19 Next single step the routine through to the end Check to see if the program is working as expected You should get the same value for z as in Lab2a End of Exercise C28x Programming Development Environment 2 29 ...

Page 48: ... 1 cinit cinit FLASH PAGE 0 FLASH PAGE 0 stack M0SARAM PAGE 1 stack M0SARAM PAGE 1 Exercise 2a Exercise 2a Solution Solution Lab 2a Solution Lab 2a Solution lab2 cmd lab2 cmd MEMORY MEMORY PAGE 0 PAGE 0 Program Space Program Space H0SARAM org 0x3F8000 H0SARAM org 0x3F8000 len len 0x2000 0x2000 PAGE 1 PAGE 1 Data Space Data Space M0SARAM org 0x000000 M0SARAM org 0x000000 len len 0x400 0x400 M1SARAM...

Page 49: ...er this set of files is known as the header files Eventually the entire collection will be replaced with a CCS add in called the Chip Support Library CSL At that time there will be a GUI interface used via CCS s config tool Registers and the bit fields are represented by structures C functions and macros are used to initialize or modify the structures registers In this module you will learn how to...

Page 50: ... 3 3 Naming Conventions 3 6 Example of Peripheral Structure h file 3 7 Mapping Structures to Memory 3 8 Linker Command File 3 8 F281x C Code Header Files 3 9 h Definition Files 3 10 Global Variable Definition File 3 11 Peripheral Specific Routines 3 12 Example Usage Flow 3 13 Summary 3 15 3 2 C28x Peripheral Registers Header Files ...

Page 51: ...ient code in many cases Advantages Advantages Simple fast and easy to type Simple fast and easy to type Variable names exactly match register names easy Variable names exactly match register names easy to remember to remember Structure Approach to C Coding Structure Approach to C Coding void main void void main void AdcRegs AdcRegs ADCTRL1 all 0x1234 ADCTRL1 all 0x1234 write entire register write ...

Page 52: ...Structure Approach to C Coding The CCS Watch Window using Structures The CCS Watch Window using Structures The CCS Watch Window using define The CCS Watch Window using define 3 4 C28x Peripheral Registers Header Files ...

Page 53: ...ents Easy to read the code w o comments Bit mask built Bit mask built in to structure in to structure Compare with the define Approach Compare with the define Approach The define approach relies heavily on less The define approach relies heavily on less efficient efficient pointers for random memory access and often does not pointers for random memory access and often does not take advantage of C2...

Page 54: ... half MSW half MSW Access high 16 Access high 16 bits of 32 bits of 32 bit register bit register PeripheralName PeripheralName RegisterName RegisterName bit bit FieldName FieldName Access specified bit fields of register Access specified bit fields of register Notes 1 Notes 1 PeripheralName PeripheralName are assigned by TI and found in the DSP281x header files are assigned by TI and found in the ...

Page 55: ...2 Emulation suspend mode Uint16 SUSMOD 2 13 12 Emulation suspend mode Uint16 RESET 1 Uint16 RESET 1 14 ADC reset 14 ADC reset Uint16 rsvd3 1 Uint16 rsvd3 1 15 reserved 15 reserved Allow access to the bit fields or entire register Allow access to the bit fields or entire register union ADCTRL1_REG union ADCTRL1_REG Uint16 all Uint16 all struct struct ADCTRL1_BITS bit ADCTRL1_BITS bit ADC External R...

Page 56: ...TA_SECTION pragma pragma used to assign a unique linker section used to assign a unique linker section name to the peripheral structure name to the peripheral structure Linker command file maps the unique peripheral section Linker command file maps the unique peripheral section name to the physical memory address name to the physical memory address DSP281x_ DSP281x_GlobalVariableDefs GlobalVariabl...

Page 57: ... cmd Æ Æ linker command files linker command files DSP281x_headers DSP281x_headers gel gel Æ Æ gel files for CCS gel files for CCS DSP281x_examples DSP281x_examples Æ Æ example programs example programs doc doc Æ Æ documentation documentation TI has done all of the work for you TI has done all of the work for you A peripheral is programmed by writing values to a set of registers Sometimes individu...

Page 58: ...n peripheral and system registers peripheral and system registers DSP281x_Device h DSP281x_Device h main include file main include file will include all other h files will include all other h files include include DSP281x_Device h DSP281x_Device h DSP281x_Device h DSP281x_Device h DSP281x_ DSP281x_DevEmu DevEmu h h DSP281x_ DSP281x_SysCtrl SysCtrl h h DSP281x_ DSP281x_PieCtrl PieCtrl h h DSP281x_ ...

Page 59: ...nes all variables to use h files DATA_SECTION DATA_SECTION pragma pragma used to used to define data section for each define data section for each peripheral structure peripheral structure Linker will link each structure to the Linker will link each structure to the physical address of the peripheral in physical address of the peripheral in memory memory Add Add DSP281x_ DSP281x_GlobalVariableDefs...

Page 60: ...281x_DefaultIsr DefaultIsr c c Workshop lab files based on above files with modifications Workshop lab files based on above files with modifications Other files included in the packet Other Files in Packet Other Files in Packet Linker Linker cmd cmd files files DSP281x_Headers_BIOS DSP281x_Headers_BIOS cmd cmd DSP281x_Headers_ DSP281x_Headers_nonBIOS nonBIOS cmd cmd Contains memory allocation for ...

Page 61: ...shell ISR routine in the DSP281x_DefaultIsr c file Disable and clear all CPU interrupts DINT IER 0x0000 IFR 0x0000 Initialize Pie Control Registers To Default State This function is found in the DSP281x_PieCtrl c file InitPieCtrl Initialize the PIE Vector Table To a Known State This function is found in DSP281x_PieVect c This function populates the PIE vector table with pointers to the shell ISR f...

Page 62: ...NT1 Enable TINT0 in the PIE Group 1 interrupt 7 PieCtrlRegs PIEIER1 bit INTx7 1 Enable global Interrupts and higher priority real time debug events EINT Enable Global interrupt INTM ERTM Enable Global realtime interrupt DBGM Step 6 IDLE loop Just sit and loop forever optional for Step 7 Insert all local Interrupt Service Routines ISRs and functions here If local ISRs are used reassign vector addre...

Page 63: ... Easy to use Generates most efficient Code Generates most efficient Code Increases Effectiveness of CCS Increases Effectiveness of CCS Watch Window Watch Window TI has already done all the work TI has already done all the work Download literature SPRC097 from www Download literature SPRC097 from www ti ti com com C28x Peripheral Registers Header Files 3 15 ...

Page 64: ...Summary 3 16 C28x Peripheral Registers Header Files ...

Page 65: ...ves Learning Objectives Learning Objectives Describe the C28x reset process Describe the C28x reset process and post and post reset device state reset device state List the event sequence during an List the event sequence during an interrupt interrupt Describe the C28x interrupt Describe the C28x interrupt structure structure C28x Reset and Interrupts 4 1 ...

Page 66: ...odule Topics 4 2 Core Interrupt Lines 4 3 Reset 4 3 Reset Bootloader 4 5 Interrupt Sources 4 7 Interrupt Processing 4 7 Peripheral Interrupt Expansion PIE 4 9 PIE Interrupt Vector Table 4 10 Interrupt Response and Latency 4 13 4 2 C28x Reset and Interrupts ...

Page 67: ...14 maskable maskable interrupts interrupts INT1 INT1 INT14 INT14 INT1 INT1 INT2 INT2 INT3 INT3 INT4 INT4 INT5 INT5 INT6 INT6 INT7 INT7 INT8 INT8 INT9 INT9 INT10 INT10 INT11 INT11 INT12 INT12 INT13 INT13 INT14 INT14 RS RS NMI NMI Reset C28x Reset Sources C28x Reset Sources Watchdog Timer Watchdog Timer RS pin active RS pin active To RS pin To RS pin RS RS C28x Core C28x Core C28x Reset and Interrup...

Page 68: ...ode off Overflow mode off TC 0 TC 0 test control flag test control flag C 0 C 0 carry bit carry bit Z 0 Z 0 zero flag zero flag Status Register 1 ST1 Status Register 1 ST1 INTM 1 INTM 1 Disable all maskable interrupts Disable all maskable interrupts global global DBGM 1 DBGM 1 Emulation access events disabled Emulation access events disabled PAGE0 0 PAGE0 0 Stack addressing mode enabled Direct add...

Page 69: ... is status bit in XINTFCNF2 register MP MC is status bit in XINTFCNF2 register XMPNMC only sampled at reset XMPNMC only sampled at reset Bootloader Bootloader sets sets OBJMODE 1 OBJMODE 1 AMODE 0 AMODE 0 Bootloader Bootloader Options Options GPIO pins GPIO pins F4 F12 F3 F2 F4 F12 F3 F2 1 x x x jump to 1 x x x jump to FLASH FLASH address 0x3F 7FF6 address 0x3F 7FF6 0 0 1 0 jump to 0 0 1 0 jump to...

Page 70: ...F 8000 0x3F 8000 0x3F F000 0x3F F000 0x3F FFC0 0x3F FFC0 Boot ROM 4K Boot ROM 4K BROM vector 32 BROM vector 32 0x3F FC00 0x3F FC00 Boot Code Boot Code RESET RESET Execution Entry Execution Entry Point Determined Point Determined By GPIO Pins By GPIO Pins Bootloading Bootloading Routines Routines SPI SCI SPI SCI A A Parallel Load Parallel Load 0x3F FC00 0x3F FC00 4 6 C28x Reset and Interrupts ...

Page 71: ...INT0 TINT0 Interrupt Processing A valid signal on a specific interrupt line causes the latch A valid signal on a specific interrupt line causes the latch to display a 1 in the appropriate bit to display a 1 in the appropriate bit Maskable Maskable Interrupt Processing Interrupt Processing Conceptual Core Overview Conceptual Core Overview 1 1 0 0 1 1 IFR IFR Latch Latch INT1 INT1 INT2 INT2 INT14 IN...

Page 72: ...rn extern cregister cregister volatile unsigned volatile unsigned int int IFR IFR IFR 0x0008 IFR 0x0008 set INT4 in IFR set INT4 in IFR IFR 0xFFF7 IFR 0xFFF7 clear INT4 in IFR clear INT4 in IFR Interrupt Enable Register IER Interrupt Enable Register IER RTOSINT RTOSINT DLOGINT DLOGINT INT14 INT14 INT13 INT13 INT12 INT12 INT11 INT11 INT10 INT10 INT9 INT9 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 ...

Page 73: ...28x Core Core 28x Core Interrupt logic 28x Core Interrupt logic PIE module for 96 Interrupts PIE module for 96 Interrupts INT1 x interrupt group INT1 x interrupt group INT2 x interrupt group INT2 x interrupt group INT3 x interrupt group INT3 x interrupt group INT4 x interrupt group INT4 x interrupt group INT5 x interrupt group INT5 x interrupt group INT6 x interrupt group INT6 x interrupt group IN...

Page 74: ...nowledge the PIE group 3 PieCtrlRegs PIECTRL bit ENPIE 1 enable the PIE PIE Interrupt Vector Table Prio Prio Vector Vector Offset Offset Default Interrupt Vector Table at Reset Default Interrupt Vector Table at Reset Memory Memory 0 0 BROM Vectors BROM Vectors 64 W 64 W 0x3F FFC0 0x3F FFC0 0x3F FFFF 0x3F FFFF PIE Vectors PIE Vectors 256 W 256 W 0x00 0D00 0x00 0D00 4 4 2 2 3 3 DlogInt DlogInt RtosI...

Page 75: ... 0x00 0D02 INT1 re INT1 re mapped below mapped below re re mapped below mapped below INT12 0x00 0D18 INT12 re INT12 0x00 0D18 INT12 re mapped below mapped below RESET and INT1 INT12 vector locations are Re mapped F281x PIE Interrupt Assignment Table F281x PIE Interrupt Assignment Table INTx 8 INTx 8 INTx 7 INTx 7 INTx 6 INTx 6 INTx 5 INTx 5 INTx 4 INTx 4 INTx 3 INTx 3 INTx 2 INTx 2 INTx 1 INTx 1 I...

Page 76: ...S PIE Vector Table PIE Vector Table 256 Word RAM 256 Word RAM 0x00 0D00 0x00 0D00 0DFF 0DFF RESET RESET Reset Vector 0x3F FFCO Boot Reset Vector 0x3F FFCO Boot ROM Code ROM Code Flash Entry Point 0x3F 7FF6 LB _c_int00 Flash Entry Point 0x3F 7FF6 LB _c_int00 User Code Start _c_int00 User Code Start _c_int00 MPNMC 0 on MPNMC 0 on chip ROM memory chip ROM memory Reset Vector 0x3F FFCO _c_int00 Reset ...

Page 77: ...cy Latency Latency Depends on wait states ready INTM etc Depends on wait states ready INTM etc Maximum latency Maximum latency Recognition Recognition delay 3 SP delay 3 SP alignment 1 alignment 1 vector placed vector placed in PC in PC 4 4 Minimum latency to when real work occurs in the ISR Minimum latency to when real work occurs in the ISR Internal interrupts 14 cycles Internal interrupts 14 cy...

Page 78: ...Interrupt Sources 4 14 C28x Reset and Interrupts ...

Page 79: ...igital I O ports and the EALLOW protected registers will be covered Learning Objectives Learning Objectives Learning Objectives OSC PLL Clock Module OSC PLL Clock Module Watchdog Timer Watchdog Timer Low Power Modes Low Power Modes General Purpose Digital I O General Purpose Digital I O EALLOW Protected Registers EALLOW Protected Registers C28x System Initialization 5 1 ...

Page 80: ...Initialization 5 1 Module Topics 5 2 Oscillator PLL Clock Module 5 3 Watchdog Timer 5 5 Low Power Modes 5 9 General Purpose Digital I O 5 11 EALLOW Protected Registers 5 14 Lab 5 System Initialization 5 15 5 2 C28x System Initialization ...

Page 81: ...t PLL Select X1 CLKIN X1 CLKIN X2 X2 XTAL OSC XTAL OSC Watchdog Watchdog Module Module 2 2 PLLCLK PLLCLK OSCCLK OSCCLK C28x C28x Core Core CLKIN CLKIN MUX MUX XF_XPLLDIS XF_XPLLDIS 0 0 1 1 SYSCLKOUT SYSCLKOUT HISPCP HISPCP LOSPCP LOSPCP HSPCLK HSPCLK LSPCLK LSPCLK default default The OSC PLL clock module provides all the necessary clocking signals for C28x devices The PLL has a 4 bit ratio control...

Page 82: ...s reducing power consumption High Low High Low Speed Peripheral Clock Speed Peripheral Clock Prescaler Prescaler Registers Registers HISPCP 0x00701A LOSPCP 0x00701B HISPCP 0x00701A LOSPCP 0x00701B lab file lab file SysCtrl SysCtrl c c 0 0 1 1 2 2 15 15 3 3 HSPCLK0 HSPCLK0 HSPCLK1 HSPCLK1 HSPCLK2 HSPCLK2 reserved 0 0 1 1 2 2 15 15 3 3 LSPCLK0 LSPCLK0 LSPCLK1 LSPCLK1 LSPCLK2 LSPCLK2 reserved H LSPCL...

Page 83: ...timer provides a safeguard against CPU crashes by automatically initiating a reset if it is not serviced by the CPU at regular intervals In motor control applications this helps protect the motor and drive electronics when control is lost due to a CPU lockup Any CPU reset will revert the PWM outputs to a high impedance state which should turn off the power converters in a properly designed system ...

Page 84: ... Pulse WDRST WDRST WDINT WDINT SCSR 1 SCSR 1 WDENINT WDENINT SCSR 0 SCSR 0 WDOVERRIDE WDOVERRIDE WDPS FRC C28x timeout Bits rollover period 150 MHz 00x 1 4 37 ms 010 2 8 74 ms 011 4 17 48 ms 100 8 34 96 ms 101 16 69 92 ms 110 32 139 84 ms 111 64 279 68 ms WDPS WDPS FRC FRC C28x timeout C28x timeout Bits Bits rollover rollover period 150 MHz period 150 MHz 00x 00x 1 4 37 ms 1 4 37 ms 010 2 8 74 ms ...

Page 85: ...hdog Resetting the Watchdog WDKEY 0x007025 WDKEY 0x007025 lab file lab file SysCtrl SysCtrl c c Allowable write values Allowable write values 55h 55h counter enabled for reset on next AAh write counter enabled for reset on next AAh write AAh AAh counter set to zero if reset enabled counter set to zero if reset enabled Writing any other value immediately triggers Writing any other value immediately...

Page 86: ...rol and Status Register System Control and Status Register SCSR 0x007022 SCSR 0x007022 lab file lab file SysCtrl SysCtrl c c WD Override protect bit WD Override protect bit After RESET After RESET bit gives user ability to disable WD by bit gives user ability to disable WD by setting WDDIS bit 1 in WDCR setting WDDIS bit 1 in WDCR clear only bit and defaults to 1 after reset clear only bit and def...

Page 87: ... c c 0 0 1 1 7 7 2 2 15 15 8 8 LPM0 LPM0 LPM1 LPM1 QUALSTDBY QUALSTDBY reserved Low Power Mode Entering Low Power Mode Entering 1 Set LPM bits 1 Set LPM bits 2 Enable desired exit interrupt s 2 Enable desired exit interrupt s 3 Execute IDLE instruction 3 Execute IDLE instruction 4 The Power down sequence of the hardware 4 The Power down sequence of the hardware depends on LP mode depends on LP mod...

Page 88: ...TRIP T1CTRIP C3TRIP C3TRIP T4CTRIP T4CTRIP C4TRIP C4TRIP C1TRIP C1TRIP C6TRIP C6TRIP SCIRXA SCIRXA CANRXA CANRXA IDLE IDLE STANDBY STANDBY HALT HALT RESET RESET yes yes yes yes yes yes External External or or Wake up Wake up Interrupts Interrupts yes yes yes yes no no yes yes no no no no Exit Exit Interrupt Interrupt Low Power Low Power Mode Mode Enabled Enabled Peripheral Peripheral Interrupts In...

Page 89: ...F4 SCITXDA GPIOF5 SCIRXDA GPIOF5 SCIRXDA GPIOF6 CANTXA GPIOF6 CANTXA GPIOF7 CANRXA GPIOF7 CANRXA GPIOF8 MCLKXA GPIOF8 MCLKXA GPIOF9 MCLKRA GPIOF9 MCLKRA GPIOF10 MFSXA GPIOF10 MFSXA GPIOF11 MFSRA GPIOF11 MFSRA GPIOF12 MDXA GPIOF12 MDXA GPIOF13 MDRA GPIOF13 MDRA GPIOF14 XF GPIOF14 XF GPIO G GPIO G GPIOG4 SCITXDB GPIOG4 SCITXDB GPIOG5 SCIRXDB GPIOG5 SCIRXDB Note Note GPIOxx GPIOxx are pin are pin fun...

Page 90: ...2 0x0070C2 GPAQUAL GPAQUAL GPIO A Input Qualification Control Register GPIO A Input Qualification Control Register 0x0070C4 0x0070C4 GPBMUX GPBMUX GPIO B GPIO B Mux Mux Control Register Control Register 0x0070C5 0x0070C5 GPBDIR GPBDIR GPIO B Direction Control Register GPIO B Direction Control Register 0x0070C6 0x0070C6 GPBQUAL GPBQUAL GPIO B Input Qualification Control Register GPIO B Input Qualif...

Page 91: ...0070EE 0x0070EE GPDCLEAR GPDCLEAR GPIO D Clear Register GPIO D Clear Register 0x0070EF 0x0070EF GPDTOGGLE GPDTOGGLE GPIO D Toggle Register GPIO D Toggle Register 0x0070F0 0x0070F0 GPEDAT GPEDAT GPIO E Data Register GPIO E Data Register 0x0070F1 0x0070F1 GPESET GPESET GPIO E Set Register GPIO E Set Register 0x0070F2 0x0070F2 GPECLEAR GPECLEAR GPIO E Clear Register GPIO E Clear Register 0x0070F3 0x0...

Page 92: ...e Note SysCtrlRegs SysCtrlRegs WDKEY 0xAA is located in an interrupt service routine WDKEY 0xAA is located in an interrupt service routine Lab 5 Procedure Lab 5 Procedure System Initialization System Initialization LAB5 files have been provided as a starting point LAB5 files have been provided as a starting point Modify LAB5 files to Modify LAB5 files to Part 1 Part 1 Disable the watchdog Disable ...

Page 93: ...ction and a 1 setting for peripheral function The first part of the lab exercise will setup the system initialization and test the watchdog operation by having the watchdog cause a reset In the second part of the lab exercise the PIE vectors will be added and tested by using the watchdog to generate an interrupt This lab will make use of the DSP281x C code header files to simplify the programming ...

Page 94: ...ches to address 0x3F8000 upon bootloader completion Modify the configuration file lab cdb to create a new memory block named BEGIN_H0 base 0x3F8000 length 0x0002 space code Uncheck the create a heap in memory box You will also need to modify the existing memory block H0SARAM to avoid any overlaps with this new memory block Setup System Initialization 4 Modify SysCtrl c to implement the system init...

Page 95: ...tSysCtrl function to enable the watchdog WDCR This will enable the watchdog to function and cause a reset Save the file and click the Build button Then reset the DSP by clicking on Debug Reset CPU Under Debug on the menu bar click Go Main 13 Place the cusor in the main loop section right click the mouse key and select Run To Cursor 14 Run your code Where did your code stop Are the results as expec...

Page 96: ...plus sign to the left of Scheduling and again on the plus sign to the left of HWI Hardware Interrupt Service Routine Manager Click the plus sign to the left of PIE INTERRUPTS Locate the interrupt location for the watchdog Right click select Properties and type _WAKEINT_ISR with a leading underscore in the function field Click OK and save all updates Build and Load 22 Save all changes to the files ...

Page 97: ...it Therefore sequential as well as simultaneous sampling is supported Also the ADC system features programmable auto sequence conversions with 16 results registers Start of conversion SOC can be performed by an external trigger software or an Event Manager event Learning Objectives Learning Objectives Learning Objectives Understand the operation of Understand the operation of Analog Analog to to D...

Page 98: ...Topics 6 2 Analog to Digital Converter 6 3 Analog to Digital Converter Registers 6 5 Example Sequencer Start Stop Operation 6 10 ADC Conversion Result Buffer Register 6 11 Numerical Format 6 12 Lab 6 Analog to Digital Converter 6 13 6 2 C28x Analog to Digital Converter ...

Page 99: ...mode Sequencer mode 12 12 bit A D bit A D Converter Converter Software Software EVA EVA Ext Pin Ext Pin ADCSOC ADCSOC Result Result Select Select Result MUX Result MUX RESULT0 RESULT0 RESULT1 RESULT1 RESULT7 RESULT7 Result Result Select Select RESULT8 RESULT8 RESULT9 RESULT9 RESULT15 RESULT15 CHSEL00 CHSEL00 state 0 state 0 CHSEL01 CHSEL01 state 1 state 1 CHSEL02 CHSEL02 state 2 state 2 CHSEL07 CH...

Page 100: ...individually addressable result registers Multiple trigger sources for start Multiple trigger sources for start of of conversion conversion External trigger S W and Event Manager events External trigger S W and Event Manager events F2812 ADC Clocking Example F2812 ADC Clocking Example CLKIN CLKIN 30 MHz 30 MHz HSPCLK HSPCLK 150 MHz 150 MHz ADCCLKPS bits ADCTRL3 ADCTRL3 0011b 0011b FCLK FCLK 25 MHz...

Page 101: ...06 ADCCHSELSEQ4 0x007106 ADC Channel Select Sequencing Control Register 4 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x007107 ADC ADCASEQSR 0x007107 ADC Autosequence Autosequence Status Register Status Register ADCRESULT0 ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0 0x007108 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x007109 ADC Conversion Result Buffer Regi...

Page 102: ...Time dependent on the Conversion Clock Clock Prescale Prescale bit Bit 7 CPS bit Bit 7 CPS ADC Control Register 1 ADC Control Register 1 Lower Byte Lower Byte ADCTRL1 0x007100 ADCTRL1 0x007100 lab file lab file Adc Adc c c 7 7 6 6 5 5 4 4 2 2 0 0 1 1 CPS CPS CONT_RUN CONT_RUN reserved Sequencer Mode Sequencer Mode 0 dual mode 0 dual mode 1 cascaded mode 1 cascaded mode 3 3 Continuous Run Continuou...

Page 103: ...terrupt every EOS 1 interrupt every other EOS 1 interrupt every other EOS ADC Control Register 2 ADC Control Register 2 Lower Byte Lower Byte ADCTRL2 0x007101 ADCTRL2 0x007101 lab file lab file Adc Adc c c 7 7 6 6 5 5 4 4 2 2 0 0 1 1 EXT_SOC EXT_SOC _SEQ1 _SEQ1 RST_SEQ2 RST_SEQ2 External SOC SEQ1 External SOC SEQ1 0 no action 0 no action 1 start by signal 1 start by signal from ADCSOC pin from ADC...

Page 104: ...ered down 1 powered up 1 powered up Maximum Conversion Channels Register Maximum Conversion Channels Register ADCMAXCONV 0x007102 ADCMAXCONV 0x007102 lab file lab file Adc Adc c c MAX_ MAX_ CONV 2_2 CONV 2_2 MAX_ MAX_ CONV 2_1 CONV 2_1 MAX_ MAX_ CONV 2_0 CONV 2_0 MAX_ MAX_ CONV 1_3 CONV 1_3 MAX_ MAX_ CONV 1_2 CONV 1_2 MAX_ MAX_ CONV 1_1 CONV 1_1 MAX_ MAX_ CONV 1_0 CONV 1_0 reserved Cascaded Mode C...

Page 105: ...0 0 0x007103 0x007103 CONV03 CONV02 CONV01 CONV00 CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1 ADCCHSELSEQ1 0x007104 0x007104 CONV07 CONV06 CONV05 CONV04 CONV07 CONV06 CONV05 CONV04 ADCCHSELSEQ2 ADCCHSELSEQ2 0x007105 0x007105 CONV11 CONV10 CONV09 CONV08 CONV11 CONV10 CONV09 CONV08 ADCCHSELSEQ3 ADCCHSELSEQ3 0x007106 0x007106 CONV15 CONV14 CONV13 CONV12 CONV15 CONV14 CONV13 CONV12 ADCCHSELSEQ4 ADCCHSELS...

Page 106: ...t to 2 and Channel Select Sequencing Control Registers are set to gisters are set to Once reset and initialized SEQ1 waits for a trigger Once reset and initialized SEQ1 waits for a trigger First trigger three conversions performed CONV00 I First trigger three conversions performed CONV00 I1 1 CONV01 I CONV01 I2 2 CONV02 I CONV02 I3 3 MAX_CONV1 value is reset to 2 unless changed by software MAX_CON...

Page 107: ...isters With analog input 0V to 3V we have With analog input 0V to 3V we have analog volts analog volts converted value converted value RESULTx RESULTx 3 0 3 0 FFFh FFFh 1111 1111 1111 0000 1111 1111 1111 0000 1 5 1 5 7FFh 7FFh 0111 1111 1111 0000 0111 1111 1111 0000 0 00073 0 00073 1h 1h 0000 0000 0001 0000 0000 0000 0001 0000 0 0 0h 0h 0000 0000 0000 0000 0000 0000 0000 0000 MSB MSB 0 0 1 1 2 2 3...

Page 108: ...n void void main void Uint16 value Uint16 value unsigned unsigned value value AdcRegs AdcRegs ADCRESULT0 4 ADCRESULT0 4 What About Signed Input Voltages What About Signed Input Voltages Example Example 1 5 V 1 5 V V Vin in 1 5 V 1 5 V 1 Add 1 5 volts to analog input 1 Add 1 5 volts to analog input V Vin in 1 5V 1 5V Input Input Ch x Ch x V VDD DD GND GND V VDDA DDA ADCLO ADCLO R R R R R R R R R R ...

Page 109: ...o initiate an ADC start of conversion SOC 1 Using software a SOC_SEQ1 SOC_SEQ2 bit in ADCTRL2 causes an SOC upon completion of the current conversion if the ADC is currently idle an SOC occurs immediately 2 Automatically triggered on user selectable event manager conditions a GP Timer 1 or 2 EVA 3 or 4 EVB underflow e g timer count 0 b GP Timer 1 or 2 EVA 3 or 4 EVB period match c GP Timer 1 or 2 ...

Page 110: ...DC on set to trigger ADC on period match period match set the clock set the clock prescaler prescaler enable the timer enable the timer Main Loop Main Loop loop B loop loop B loop ADC ISR ADC ISR context save context save read the ADC result read the ADC result write to result buffer write to result buffer adjust the buffer pointer adjust the buffer pointer toggle the GPIO pin toggle the GPIO pin ...

Page 111: ... location for the ADC interrupt ADCINT and fill in the following information PIE group within group This information will be used in the next step 5 Modify the end of Adc c to do the following enable the ADCINT interrupt in the PIE Hint use the PieCtrlRegs structure enable core INT1 IER register 6 Open and inspect DefaultIsr_5_6_7 c This file contains the ADC interrupt service routine 7 Modify the...

Page 112: ... halt it after a few seconds Verify that the ADC results buffer contains the expected value of 0x0FFF 14 Adjust the connector wire to connect the ADCINA0 pin P9 2 to IOPA1 pin P8 10 on the eZdsp Then run the code again and halt it after a few seconds Examine the contents of the ADC results buffer the contents should be alternating 0x0000 and 0x0FFF values Are the contents what you expected 15 Open...

Page 113: ...eeping critical parts of your system operating e g commutation and current loops in motor control We will only be utilizing capability 1 above during the workshop Capability 2 is a particularly advanced feature and will not be covered in the workshop 18 Reset the DSP and enable real time mode by selecting Debug Real time Mode 19 A message box will appear Select YES to enable debug events This will...

Page 114: ...the DSP Open and inspect DefaultIsr_5_6_7 c Notice that the global variable DEBUG_TOGGLE is used to control the toggling of the GPIOA1 pin This is the pin being read with the ADC Highlight DEBUG_TOGGLE with the mouse right click and select Add to Watch Window The global variable DEBUG_TOGGLE should now be in the watch window with a value of 1 Run the code in real time mode and change the value to ...

Page 115: ...ionality of EVA will be explained Learning Objectives Learning Objectives Learning Objectives Pulse Width Modulation PWM Review Pulse Width Modulation PWM Review Generate PWM with the Event Manager Generate PWM with the Event Manager General General Purpose Timer Purpose Timer Compare Units Compare Units Explain other Event Manager functions Explain other Event Manager functions Capture Units Capt...

Page 116: ... via General Purpose Timer Compares 7 16 GP Timer Compare PWM Exercise 7 17 Compare Units 7 18 Compare Unit Registers 7 19 Hardware Dead Band Compare Units only 7 22 Power Drive Protection 7 25 Capture Units 7 26 Capture Units Registers 7 29 Quadrature Encoder Pulse QEP 7 32 QEP Initialization with GP Timer 2 EVA 7 34 Lab 7 Event Manager 7 36 GP Timer Compare PWM Exercise Solution 7 42 7 2 C28x Ev...

Page 117: ...MUX QEP QEP Circuit Circuit Output Logic Output Logic Output Logic Output Logic EV Control Registers Logic EV Control Registers Logic Reset Reset PIE PIE TCLKINA TDIRA TCLKINA TDIRA 2 2 ADC Start ADC Start Data Bus Data Bus CLK CLK DIR DIR T1PWM_T1CMP T1PWM_T1CMP T2PWM_T2CMP T2PWM_T2CMP PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 PWM4 PWM4 PWM5 PWM5 PWM6 PWM6 CAP1 QEP1 CAP1 QEP1 CAP2 QEP2 CAP2 QEP2 CAP3 QEPI1 C...

Page 118: ...e Amplitude Modulation Modulation fixed width variable amplitude fixed width variable amplitude Pulse width modulation PWM is a method for representing an analog signal with a digital approximation The PWM signal consists of a sequence of variable width constant amplitude pulses which contain the same total energy as the original analog signal This property is valuable in digital motor control as ...

Page 119: ...hing devices are transistors Power switching devices are transistors Difficult to control in proportional region Difficult to control in proportional region Easy to control in saturated region Easy to control in saturated region PWM is a digital signal PWM is a digital signal easy for DSP to output easy for DSP to output PWM approx PWM approx of desired of desired signal signal DC Supply DC Supply...

Page 120: ... Period Period Compare Compare T Tpwm pwm T Tcmp cmp Pin Pin active high active high Caused by Period match Caused by Period match toggle output in toggle output in Asym Asym mode only mode only Caused by Compare match Caused by Compare match T TPWM PWM 7 6 C28x Event Manager ...

Page 121: ...cies can be independently selected as follows 4 PWM freq1 1 PWM freq2 Of course frequency 1 need not differ from frequency 2 In addition three PWM signals may be generated which are compliments of three of the above listed five i e full compare units This forms three complimentary pairs of PWM and is intended for use as input to a three phase power converter Two different compare types exist on ea...

Page 122: ...Output Logic Output Logic EV Control Registers Logic EV Control Registers Logic Reset Reset PIE PIE TCLKINA TDIRA TCLKINA TDIRA 2 2 ADC Start ADC Start Data Bus Data Bus CLK CLK DIR DIR T1PWM_T1CMP T1PWM_T1CMP T2PWM_T2CMP T2PWM_T2CMP PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 PWM4 PWM4 PWM5 PWM5 PWM6 PWM6 CAP1 QEP1 CAP1 QEP1 CAP2 QEP2 CAP2 QEP2 CAP3 QEPI1 CAP3 QEPI1 The GP Timers provide a time base for the op...

Page 123: ...that the period register buffer is static in that if no change in the current period value is desired one is not required to write the same value to the buffer on successive timer cycles The clocking signal for each GP Timer can be individually selected as either the internal CPU clock or the external TCLKINA B pin In addition the QEP outputs can be selected for clocking GP Timers The external TDI...

Page 124: ...3 TxCON 3 2 00 reload 2 00 reload TxCMPR TxCMPR on underflow on underflow TxPR TxPR 3 3 TxCMPR TxCMPR 1 initially 1 initially Prescale Prescale 1 1 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 0 0 1 1 2 2 CPUCLK CPUCLK TxCNT TxCNT Reg Reg 3 3 0 0 CPU writes a 2 to CPU writes a 2 to compare reg buffer compare reg buffer anytime here anytime here TxCMPR TxCMPR 2 is loaded here 2 is loaded here TxPWM TxPWM TxCMP ...

Page 125: ...with a 1 with a 1 TxCMPR TxCMPR loads loads with a 2 with a 2 TxCMPR TxCMPR loads loads with a 1 with a 1 Used for Symmetric PWM Waveforms Used for Symmetric PWM Waveforms Seemless Seemless up down repetition up down repetition Up down count period is 2 Up down count period is 2 TxPR TxPR The procedure for GP Timer Continuous Up Down Counting is as follows User sets bit 6 of TxCON register high to...

Page 126: ...ected events 1 timer underflow TxCNT 0 2 timer underflow or period match 3 immediately The event selection is made using bits 2 and 3 of the TxCON register and allows for on the fly compare value changes Note that the compare register buffer is static in that if no change in the current compare value is desired one is not required to write the same value to the buffer on successive timer cycles Ea...

Page 127: ...c EXTCONA 0x007409 EXTCONB 0x007509 Extension Control Register EXTCONA 0x007409 EXTCONB 0x007509 Extension Control Register GP Timer Control Register A GP Timer Control Register A EVA EVA GPTCONA 0x007400 GPTCONA 0x007400 lab file lab file Ev Ev c c 15 15 14 14 13 13 12 12 10 10 9 9 8 8 7 7 T2STAT T2STAT T1STAT T1STAT T2TOADC T2TOADC T1TOADC T1TOADC GP Timer Status read GP Timer Status read only o...

Page 128: ...e Timer 1 Compare Output Enable Timer 1 Compare Output Enable T1CMPOE T1CMPOE if EXTCONA 0 1 if EXTCONA 0 1 0 disable hi 0 disable hi Z Z 1 enable 1 enable Timer Control Register Timer Control Register EVA EVA T1CON 0x007404 T2CON 0x007408 T1CON 0x007404 T2CON 0x007408 lab file lab file Ev Ev c c FREE FREE 15 15 14 14 13 13 12 12 10 10 8 8 SOFT SOFT TMODE0 TMODE0 TPS0 TPS0 TPS1 TPS1 TPS2 TPS2 9 9 ...

Page 129: ...re Register Reload Condition 00 when counter equals zero underflow 00 when counter equals zero underflow 01 when counter equals zero or period 01 when counter equals zero or period reg reg 10 immediately 10 immediately 11 reserved 11 reserved Timer Compare Operation Enable Timer Compare Operation Enable 0 disable 0 disable 1 enable 1 enable Period Register Select Period Register Select 0 use own p...

Page 130: ...resolution can be computed once the period register value is determined The largest power of 2 is determined that is less than or close to the period value As an example if asymmetric was 1000 and symmetric was 500 then Asymmetric PWM approx 10 bit resolution since 210 1024 1000 Symmetric PWM approx 9 bit resolution since 29 512 500 PWM duty cycle Duty cycle calculations are simple provided one re...

Page 131: ...r counter clocked by 10 ns CPU clock Use the Use the 1 1 prescale prescale option option 25 duty cycle initially 25 duty cycle initially Use GP Timer Compare 1 with PWM output active high Use GP Timer Compare 1 with PWM output active high T2PWM T2CMP pins forced low T2PWM T2CMP pins forced low Determine the initialization values needed in the GPTCONA Determine the initialization values needed in t...

Page 132: ...P PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 PWM4 PWM4 PWM5 PWM5 PWM6 PWM6 CAP1 QEP1 CAP1 QEP1 CAP2 QEP2 CAP2 QEP2 CAP3 QEPI1 CAP3 QEPI1 Each event manager EVA and EVB has three compare units Each compare unit has two associated PWM outputs They have capabilities beyond the GP timer compares and feature programmable hardware deadband The time base for the compare units is provided by GP timer 1 for EVA and GP ...

Page 133: ...ister 5 Compare Register 5 CMPR6 CMPR6 0x007519 0x007519 Compare Register 6 Compare Register 6 EVA EVA EVB EVB EXTCONA 0x007409 EXTCONB 0x007509 Extension Control Register EXTCONA 0x007409 EXTCONB 0x007509 Extension Control Register Compare Control Register Compare Control Register EVA EVA COMCONA 0x007411 COMCONA 0x007411 lab file lab file Ev Ev c c CENABLE CENABLE 15 15 14 14 13 13 12 12 10 10 8...

Page 134: ...ONA 0 1 0 disable 0 disable 1 enable 1 enable Full Compare 1 Full Compare 1 Output Enable Output Enable FCMP1OE FCMP1OE if EXTCONA 0 1 if EXTCONA 0 1 0 disable 0 disable 1 enable 1 enable Full Compare 3 Full Compare 3 Output Enable Output Enable FCMP3OE FCMP3OE if EXTCONA 0 1 if EXTCONA 0 1 0 disable 0 disable 1 enable 1 enable Full Compare 2 Full Compare 2 Output Enable Output Enable FCMP2OE FCMP...

Page 135: ...MP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP1ACT0 CMP1ACT1 CMP2ACT0 1 3 Pin Action on Compare CMPyACT1 0 00 force low 01 active low 10 active high 11 forced high SVRDIR 15 14 13 12 10 8 D2 D1 D0 CMP6ACT1 CMP5ACT0 CMP5ACT1 CMP6ACT0 9 11 Basic Space Vector Bits can write as 0 when SV not in use SV Rotation Direction can write as 0 when SV not in use C28x Event Manager 7 21 ...

Page 136: ... lower gates in the same phase of a power converter are open simultaneously This condition shorts the power supply and results in a large current draw Shoot through problems occur because transistors open faster than they close and because high side and low side power converter gates are typically switched in a complimentary fashion Although the duration of the shoot through current path is finite...

Page 137: ...ower circuit modification The resistor acts to limit the current rise rate towards the gate during transistor opening thus increasing the opening time When closing the transistor however current flows unimpeded from the gate via the by pass diode and closing time is therefore not affected While this passive approach offers an inexpensive solution that is independent of the control microprocessor i...

Page 138: ...e DB Timer Prescaler 000 1 100 16 001 2 101 32 010 4 110 32 011 8 111 32 DB Timer Period dead time DB period DB prescaler CPUCLK period reserved reserved reserved reserved DBTPS0 Each compare unit has its own dead band timer but shares the clock prescaler unit and the dead band period with the other compare units Dead band can be individually enabled for each compare unit by setting bits 5 6 and 7...

Page 139: ...rive Protection Power Drive Protection PDPINTA PDPINTB PDPINTA PDPINTB Interrupt latency may not protect hardware when Interrupt latency may not protect hardware when responding to over current through ISR software responding to over current through ISR software PDPINTx PDPINTx has a fast clock independent logic path has a fast clock independent logic path to high to high impedance the PWM output ...

Page 140: ... TCLKINA TDIRA 2 ADC Start Data Bus CLK DIR T1PWM_T1CMP T2PWM_T2CMP PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 CAP1 QEP1 CAP2 QEP2 CAP3 QEPI1 Each event manager EVA and EVB has three capture units and each is associated with a capture input pin Each capture unit can choose GP timer 1 or 2 for EVA and GP timer 3 or 4 for EVB as its time base The value of GP timer 1 or 2 EVA and GP timer 3 or 4 EVB is captured a...

Page 141: ...he capture unit does not suffer from this limitation since it is edge triggered and can be configured to start a conversion on either rising edges falling edges or both Second if the ADCSOC pin is held high longer than one conversion period a second conversion will be immediately initiated upon completion of the first This unwanted second conversion could still be in progress when a desired conver...

Page 142: ...vals Signal from one quadrature encoder channel Low speed velocity estimation from incr encoder Measure the time width of a pulse vk x tk tk 1 vk t xk xk 1 x Capture Units Block Diagram Capture Units Block Diagram EVA EVA Can latch on rising edge falling edge both GP Timer 1 Counter T1CNT 15 0 Edge Detect CAP3TOADC CAP1 2 3 MUX GP Timer 2 Counter T2CNT 15 0 CAPCONA 10 9 Enable CAPCONA 14 12 2 Leve...

Page 143: ...on CAPCONA 0x007420 Capture Control Register A CAPFIFOA 0x007422 Capture FIFO Status Register A CAP1FIFO 0x007423 Two Level Deep FIFO 1 Stack CAP2FIFO 0x007424 Two Level Deep FIFO 2 Stack CAP3FIFO 0x007425 Two Level Deep FIFO 3 Stack CAP1FBOT 0x007427 Bottom Register of FIFO 1 CAP2FBOT 0x007428 Bottom Register of FIFO 2 CAP3FBOT 0x007429 Bottom Register of FIFO 3 CAPCONB 0x007520 Capture Control R...

Page 144: ...before a computation proceeds e g measuring the width of a pulse If the width of the pulse is needed as soon as the pulse ends then the capture interrupt is the best option However the capture interrupt will occur after each of the two captures the first of which will waste a small number of cycles while the CPU is interrupted and then determines that it is indeed only the first capture If the wid...

Page 145: ...0x007422 CAPFIFOA 0x007422 lab file lab file Ev Ev c c 13 12 9 8 11 10 CAP3FIFO CAP2FIFO CAP1FIFO FIFOx Status 00 empty 01 one entry 10 two entries 11 three entries attempted 1st entry lost CAPxFIFO bits are automatically adjusted on a capture or FIFO read 15 14 reserved 7 0 C28x Event Manager 7 31 ...

Page 146: ...DC Start Data Bus CLK DIR T1PWM_T1CMP T2PWM_T2CMP PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 CAP1 QEP1 CAP2 QEP2 CAP3 QEPI1 The QEP circuit when enabled decodes and counts the quadrature encoded input pulses on pins CAP1 QEP1 and CAP2 QEP2 in EVA and CAP4 QEP3 and CAP5 QEP4 in EVB The QEP circuit can be used to interface with an optical encoder to get position and speed information from a rotating machine When...

Page 147: ...o sensors spaced θ 4 deg apart light source LED shaft rotation Ch A Ch B Quadrature Output from Photo Sensors θ θ 4 Incremental Optical Encoder How is Position Determined from How is Position Determined from Quadrature Quadrature Signals Signals Ch A Ch B 00 11 10 01 A B 00 01 11 10 Quadrature Decoder State Machine increment counter decrement counter Position resolution is θ 4 degrees C28x Event M...

Page 148: ...s 1 Ch A Ch B CAP1 QEP1 CAP2 QEP2 QEP decoder logic GP Timer 2 CLK DIR Index CAP3 QEPI QEPIE QEPIQUAL QEP Initialization with GP Timer 2 EVA Select Timer 2 for Capture number1 and 2 CAPCONA 9 0 for Timer 2 Optionally pre load Timer 2 counter TxCNT register Select directional up down mode for Timer 2 TxCON 12 11 11 Set T2PER register for desired timer rollover e g set the number of ticks per revolu...

Page 149: ...XTCONA 0x007409 lab file lab file Ev Ev c c INDCOE QEPIQUAL QEPIE EVSOCE reserved 1 0 2 3 15 4 Independent Compare Output Enable Mode 0 disable 1 enable QEP Index Enable 0 disable 1 enable CAP3 QEPI Index Qualification Mode 0 off 1 on EV Start of Conversion Output Enable 0 disable 1 enable C28x Event Manager 7 35 ...

Page 150: ...idth of the pulse and duty cycle of the waveform The results of this step will be viewed numerically in a memory window Lab 7 Event Manager Lab 7 Event Manager EVA EVA ADC RESULT0 data memory pointer rewind CPU copies result to buffer during ADC ISR GP Timer 2 GP Timer 2 triggers ADC SOC every 20 µs 50 kHz connector wire Compare 1 PWM Circuits Output Logic Capture 1 FIFO FIFO GP Timer 1 Event Mana...

Page 151: ...ing Timer 2 setup Save your work Build and Load 4 Save all changes to the files and click the Build button 5 Reset the DSP Run the Code PWM Waveform 6 Open a memory window to view some of the contents of the ADC results buffer The address label for the ADC results buffer is AdcBuf We will be running our code in real time mode and need to have our window continuously refresh Enable Real time Mode a...

Page 152: ...m period you can use the PC calculator program found in Microsoft Windows to do this Frequency Domain Graphing Feature of Code Composer Studio 11 Code Composer Studio also has the ability to make frequency domain plots It does this by using the PC to perform a Fast Fourier Transform FFT of the DSP data Let s make a frequency domain plot of the contents in the ADC results buffer i e the PWM wavefor...

Page 153: ... use the PieCtrlRegs structure enable core INT3 IER register 18 Open and inspect the Capture Unit 1 interrupt service routine CAPINT1_ISR in the file DefaultIsr_5_6_7 c 19 Modify the configuration file lab cdb to setup the PIE vector for the CAP1 interrupt Click on the plus sign to the left of Scheduling and again on the plus sign to the left of HWI Hardware Interrupt Service Routine Manager Click...

Page 154: ...ctive portion of the 25 duty 2 kHz PWM is 125 µsec However in Ev_7_8_9_10 c the line define ADC_sample_period 2999 gives Timer 2 a period of 3000 SYSCLKOUT cycles equivalent to 50 kHz or a 20 µsec period It would be difficult to use Timer 2 to measure the duty To understand why here is as an analogy Suppose someone hands you a stopwatch that can record only 1 minute of elapsed time before rolling ...

Page 155: ...1 pin P8 6 on the eZdsp run real time mode the code again and fully halt it after a few seconds Observe the values for CAP_rising CAP_falling and CAP_duty in a memory window Notice that CAP_duty is simply the difference between CAP_rising and CAP_falling using 16 bit modulo signed math Questions What is the value of CAP_duty in memory How does it compare with the expected value End of Exercise C28...

Page 156: ...N xx00100001000010 b xx00100001000010 b 0842h 0842h all all x s x s assigned a value of 0 assigned a value of 0 T1CMPR 100 T1CMPR 100 duty cycle T1PR 0 75 1000 750 2EEh duty cycle T1PR 0 75 1000 750 2EEh T1PR T1PR carrier period carrier period timer period timer period 2 2 2 2 1 1 1 1 10 ns 10 ns 20 20 µ µs s 1000 3E8h 1000 3E8h Counter Counter Compare Compare Period Period 50 kHz 20 50 kHz 20 µ µ...

Page 157: ...cution speed and high accuracy is needed By using these routines a user can achieve execution speeds considerable faster than equivalent code written in standard ANSI C language In addition by incorporating the ready to use high precision functions the IQmath library can shorten significantly a DSP application development time The IQmath user s guide is included in the application zip file and can...

Page 158: ... Multiplying Binary Fractions 8 9 Correcting Redundant Sign Bit 8 10 Fraction Coding 8 11 Fractional vs Integer Representation 8 12 IQmath 8 13 Floating Point Representation 8 14 IQ Fractional Representation 8 15 Traditional Q Math Approach 8 17 IQmath Approach 8 19 IQmath Library 8 24 AC Induction Motor Example 8 26 IQmath Appications and Summary 8 33 Converting ADC Results into IQ Format 8 35 La...

Page 159: ...1 4 1 2 0 1 610 111102 1 16 1 8 1 4 1 2 0 1 3010 Two s Complement Numbers Notice that binary numbers can only represent positive numbers Often it is desirable to be able to represent both positive and negative numbers The two s complement numbering system modifies the binary system to include negative numbers by making the most significant bit MSB negative Thus two s complement numbers Follow the ...

Page 160: ...mall number right justified into the larger register 2 Copy the sign bit the MSB of the original number to all unfilled bits to the left in the register sign extension Consider our two previous values copied into an 8 bit register Examples Original No 0 1 1 02 610 1 1 1 1 02 210 1 Load low 0 1 1 0 1 1 1 1 0 2 Sign Extend 0 0 0 0 0 1 1 0 4 2 6 1 1 1 1 1 1 1 0 128 64 2 2 8 4 C28x Numerical Concepts ...

Page 161: ... fill to a wider width location the sign bit is extended to fill the width of the destination the width of the destination Sign extension applies to signed numbers only Sign extension applies to signed numbers only It keeps negative numbers negative It keeps negative numbers negative Sign extension controlled by SXM bit in ST0 register Sign extension controlled by SXM bit in ST0 register When SXM ...

Page 162: ... Four Four Bit Integer Multiplication Bit Integer Multiplication 0100 0100 x 1101 x 1101 0000 00000100 0100 000 0000000 0000 00 000100 0100 1 11100 1100 1 11110100 1110100 Accumulator Accumulator Data Memory Data Memory 11110100 11110100 11110100 4 x 3 4 4 x x 3 3 12 12 12 Is there a better numbering system Is there a better numbering system In this example consider the following What are the two ...

Page 163: ...in this example Store the upper accumulator back to memory Wouldn t this create a loss of precision and a problem in how to interpret the results later Store both the upper and lower accumulator to memory This solves the above problems but creates some new ones Extra code space memory space and cycle time are used How can the result be used as the input to a subsequent calculation Is such a condit...

Page 164: ... to represent both positive and negative values the two s complement process will again be used However in the case of fractions we will not set the LSB to 1 as was the case for integers When one considers that the range of fractions is from 1 to 1 and that the only bit which conveys negative information is the MSB it seems that the MSB must be the negative ones position Since binary representatio...

Page 165: ...ial products read How shall this result be loaded into the accumulator How shall we fill the remaining bit Is this value still the expected one How can the result be stored back to memory What problems arise To read the result of the fractional multiply it is necessary to locate the binary point the base 2 equivalent of the base 10 decimal point Start by identifying the location of the binary poin...

Page 166: ...y 1 This would store values back to memory in the same Q format as the input values and with equal precision to the inputs How shall the left shift be performed Here s three methods Explicit shift Shift on store Use Product Mode shifter Correcting Redundant Sign Bit Correcting Redundant Sign Bit Correcting Redundant Sign Bit Correcting Redundant Sign Bit Correcting Redundant Sign Bit IQmath IQmath...

Page 167: ...iplying a fraction by 32K 32768 a normalized fraction is created which can be passed through the COFF tools as an integer Once in the C28x the normalized fraction looks and behaves exactly as a fraction Thus when using fractional constants in a C28x program the coder first multiplies the fraction by 32768 and uses the resulting integer rounded to the nearest whole value to represent the fraction T...

Page 168: ...x accumulator a 32 bit register adds extra range to integer calculations but this becomes a problem in storing the results back to 16 bit memory Conversely when using fractions the extra accumulator bits increase precision which helps minimize accumulative errors Since any number is accurate at best to one half of a LSB summing two of these values together would yield a worst case result of 1 LSB ...

Page 169: ...Point DSP Floating Point Algorithm C or C Natural development starts with simulation in floating point Simulation Platform i e MatLab The Fix The Fix Point Development Dilemma Point Development Dilemma The design may initially start with a simulation i e MatLab of a control algorithm which typically would be written in floating point math C or C This algorithm can be easily ported to a floating po...

Page 170: ... and f 0 then v NaN Case 2 if e 255 and f 0 then v 1 s infinity Case 3 Case 3 if 0 e 255 if 0 e 255 then v then v 1 1 s s 2 2 e e 127 127 1 f 1 f Case 4 Case 4 if e 0 and f 0 if e 0 and f 0 then v then v 1 1 s s 2 2 126 126 0 f 0 f Case 5 if e 0 and f 0 then v 1 s 0 Floating Floating Point does not Solve Point does not Solve Everything Everything Example x 10 0 0x41200000 y 0 000000238 0x347F8CF1 ...

Page 171: ...fffffffffffffff 0 31 32 bit mantissa Advantage Advantage Precision same for all numbers in an IQ format Precision same for all numbers in an IQ format Disadvantage Disadvantage Limited dynamic range compared to floating point Limited dynamic range compared to floating point 2I 2I 1 21 20 2 1 2 2 2 Q The IQmath approach enables the seamless portability of code between fixed and floating point devic...

Page 172: ...th IQmath IQmath Can Solve the Problem Can Solve the Problem I8Q24 Example x 10 0 0x0C000000 y 0 000000238 0x00000002 z 10 000000238 0x0C000002 Exact Result this example 8 16 C28x Numerical Concepts IQmath ...

Page 173: ... M i32 X i32 B Q Q in C 15 Align Binary Point For Store Traditional 32 Traditional 32 bit Q Math Approach bit Q Math Approach y y mx mx b b Y i64 M i64 X i64 B Q Q in C Note Requires support for 64 bit integer data type in compiler 24 Align Decimal Point for Add I8 Q24 M X B Y I8 Q24 I8 Q24 I16 Q48 ssssssssssssssssssI8 Q24 ssssI8 Q48 I16 Q48 sssssssssssssssssI16 Q24 I8 Q24 24 Align Decimal Point f...

Page 174: ...on on a processor containing hardware that can perform a 32x32 bit multiplication 64 bit addition and 64 bit shifts logical and arithmetic effi ciently The basic approach in traditional fixed point Q math is to align the binary point of the operands that get added to or subtracted from the multiplication result As shown in the slide the multipli cation of M and X two Q24 numbers results in a Q48 v...

Page 175: ...on below int32 Y M X B Y int64 M int64 X 24 B The slide shows the implementation of the equation on a processor containing hardware that can perform a 32x32 bit multiply 32 bit addition subtraction and 64 bit logical and arithmetic shifts efficiently The key advantage of this approach is shown by what can then be done with the C and C com piler to simplify the coding of the linear equation example...

Page 176: ... equation in C becomes Y M X B This final equation looks identical to the floating point representation It looks natural The four approaches are summarized in the table below Math Implementations Linear Equation Code 32 bit floating point math in C Y M X B 32 bit fixed point Q math in C Y int64 M int64 X int64 B 24 24 32 bit IQmath in C Y _IQ24mpy M X B 32 bit IQmath in C Y M X B Essentially the m...

Page 177: ...esult Y _IQmpy M X B 7 Cycles C28x compiler supports _ C28x compiler supports _IQmpy IQmpy intrinsic assembly code generated intrinsic assembly code generated IQmath IQmath Approach Approach It looks like floating It looks like floating point point float Y M X B Y M X B Floating Point long Y M X B Y i64 M i64 X i64 B Q Q Traditional Fix Point Q _iq Y M X B Y _IQmpy M X B IQmath In C iq Y M X B Y M...

Page 178: ... standard math library for the Texas Instruments TMS320C28x DSP fixed point processor This processor contains efficient hardware for performing 32x32 bit multiply 64 bit shifts logical and arithmetic and 32 bit add subtract operations which are ideally suited for 32 bit IQmath Some enhancements were made to the basic IQmath approach to improve flexibility They are Setting Of GLOBAL_Q Parameter Val...

Page 179: ...highlighted in the introduction we would ideally like to be able to have a single source code that can execute on a floating point or fixed point target device simply by recompiling the code The IQmath library supports this by setting a mode which selects either IQ_MATH or FLOAT_MATH This operation is performed by simply redefining the function in a header file For example if MATH_TYPE IQ_MATH def...

Page 180: ... A B float A B type type IQmath in C IQmath in C IQmath in C IQmath in C Floating Floating Point Point Operation Operation Additionally the IQmath library contains DSP library modules for filters FIR IIR and Fast Fourier Transforms FFT IFFT IQmath IQmath Library Library Conversion Functions v1 4 Conversion Functions v1 4 IQmath lib contains library of math functions IQmathLib h C header file IQmat...

Page 181: ...umbers pick one value of Q that will accommodate all cases and not worry about spending too much time optimizing Of course there is a concern on data RAM usage if numbers that could be represented in 16 bits all use 32 bits This is becoming less of an issue in today s processors because of the finer tech nology used and the amount of RAM that can be cheaply integrated However in many cases this pr...

Page 182: ...e shown later requires numerical accuracy greater then 16 bits in the control calculations The above slide is a block diagram representation of the key control blocks and their interconnec tions Essentially this system implements a Forward Control block for controlling the d q axis motor current using PID controllers and a Feedback Control block using back emf s integration with compensated voltag...

Page 183: ... v v qe qe v v qs qs cos cos_ _ang ang v v ds ds sin_ sin_ang ang AC Induction Motor Example AC Induction Motor Example Park Transform Park Transform converting to converting to IQmath IQmath C code C code include include math h math h define TWO_PI 6 28318530717959 define TWO_PI 6 28318530717959 void park_calc PARK v void park_calc PARK v float float cos cos_ _ang ang sin_ sin_ang ang sin_ sin_an...

Page 184: ...s cos_ _ang ang v v ds ds sin_ sin_ang ang extern C include IQmathLib h include IQmathCPP h IQ 6 28318530717959 iq IQsin TWO_PI v ang IQcos TWO_PI v ang As can be seen the floating point C and IQmath C code looks almost identical It is quite a simple and fast procedure to take any floating point algorithm and convert it to an IQmath algo rithm The complete system was coded using IQmath Based on an...

Page 185: ...ep change in reference speed from 0 0 to 0 5 and 1024 samples are taken The speed eventually settles to the desired reference value and the stator current exhibits a clean and stable oscillation The block diagram slide shows at which points in the control system the plots are taken from AC Induction Motor Example AC Induction Motor Example GLOBAL_Q 24 system stable GLOBAL_Q 24 system stable IQmath...

Page 186: ...otor Example GLOBAL_Q 27 system unstable GLOBAL_Q 27 system unstable IQmath speed IQmath current AC Induction Motor Example AC Induction Motor Example GLOBAL_Q 16 system unstable GLOBAL_Q 16 system unstable IQmath speed IQmath current 8 30 C28x Numerical Concepts IQmath ...

Page 187: ... coefficient used in the equations and this would be a good starting point for setting the initial GLOBAL_Q value Then through simulation or experimentation the user can reduce the GLOBAL_Q until the system resolution starts to cause instability or performance deg radation The user then has a maximum and minimum limit and a safe approach is to pick a mid point What the above analysis also confirms...

Page 188: ...e MHz used 20kHz control loop 20kHz control loop B2 ACI model cycles B2 ACI model cycles B3 Feedback control cycles B3 Feedback control cycles Benchmark Benchmark 20 9 20 9 1563 1563 1081 1081 564 564 482 482 C28x C C28x C IQmath IQmath g g 150MHz 150MHz 30 3 30 3 1137 1137 829 829 215 215 308 308 C3x C C3x C float float g g 75MHz 75MHz 23 0 23 0 1922 1922 1295 1295 321 321 627 627 C67x C C67x C f...

Page 189: ...TH One source code set for simulation vs target device One source code set for simulation vs target device Numerical resolution adjustability based on application Numerical resolution adjustability based on application requirement requirement Set in Set in IQmathLib IQmathLib h file h file define GLOBAL_Q 18 define GLOBAL_Q 18 Explicitly specify Q value Explicitly specify Q value _iq20 X Y Z _iq20...

Page 190: ...etween fixed and floating point devices Maintenance and support of one source code set from simulation to target device Adjustability of numerical resolution Q value based on application requirement Implementation of systems that may otherwise require floating point device Rapid conversion porting and implementation of algorithms 8 34 C28x Numerical Concepts IQmath ...

Page 191: ...g IQ16 to IQ format convert resulting IQ16 to IQ format temp _IQ16toIQ temp temp _IQ16toIQ temp scale by ADC full scale by ADC full scale range optional scale range optional Result _ Result _IQmpy IQmpy AdcFsVoltage AdcFsVoltage temp temp Result _ Result _IQmpy IQmpy AdcFsVoltage AdcFsVoltage _IQ16toIQ _ _IQ16toIQ _iq iq AdcRegs AdcRegs ADCRESULT0 ADCRESULT0 For uni polar ADC inputs i e 0 to 3 V i...

Page 192: ... 8 Lab 8 IQmath IQmath FIR Filter FIR Filter CPU copies result to buffer during ADC ISR ADC RESULT0 GP Timer 2 GP Timer 2 triggers ADC SOC every 20 µs 50 kHz connector wire Compare 1 PWM Circuits Output Logic GP Timer 1 Event Manager ADCINA0 data memory pointer rewind Display Display using CCS using CCS IQmath IQmath FIR Filter FIR Filter Procedure Project File Note LAB8 files have been provided a...

Page 193: ...uncomment the line that includes the IQmathLib h header file Next in the Function Prototypes section uncomment the function prototype for IQssfir the IQ math single sample FIR filter function Inspect User_8_9 cmd 5 Open and inspect User_8_9 cmd First notice that a section called IQmath is being linked to H0SARAM The IQmath section contains the IQmath library functions code Second notice that a sec...

Page 194: ...n the Code Filtered Waveform 10 Open a memory window to view some of the contents of the filtered ADC results buffer The address label for the filtered ADC results buffer is AdcBufFiltered Set the Q Value to 24 which matches the IQ format being used for this variable and the Format to 32 Bit Signed Int We will be running our code in real time mode and need to have our window continuously refresh E...

Page 195: ...the generated IQmath FIR filtered 2 kHz 25 duty cycle symmetric PWM waveform in the upper display and the unfiltered waveform generated in the previous lab exercise in the lower display Notice the shape and phase differences between the waveform plots the filtered curve has rounded edges and lags the unfiltered plot by several samples The amplitudes of both plots should run from 0 to 3 0 14 Fully ...

Page 196: ...Lab 8 IQmath FIR Filter 8 40 C28x Numerical Concepts IQmath Lab 8 Reference IQmath FIR Filter Bode Plot of Digital Low Pass Filter Coefficients 1 16 4 16 6 16 4 16 1 16 Sample Rate 50 kHz ...

Page 197: ... tools will be demonstrated Learning Objectives Learning Objectives Learning Objectives Introduction to DSP BIOS Introduction to DSP BIOS Scheduling DSP BIOS threads Scheduling DSP BIOS threads Periodic Functions Periodic Functions Real Real time Analysis Tools time Analysis Tools DSP BIOS API modules and summary DSP BIOS API modules and summary C28x Using DSP BIOS 9 1 ...

Page 198: ...sing DSP BIOS 9 1 Module Topics 9 2 Introduction to DSP BIOS 9 3 Scheduling DSP BIOS Threads 9 5 Periodic Functions 9 12 Real time Analysis Tools 9 13 DSP BIOS API Module and Summary 9 14 Lab 9 DSP BIOS 9 15 9 2 C28x Using DSP BIOS ...

Page 199: ...nt of Fully supported by TI and is a key component of TI s TI s eXpressDSP eXpressDSP real real time software technology time software technology Uses minimal MIPS and memory 2 Uses minimal MIPS and memory 2 8Kw 8Kw What is DSP BIOS What is DSP BIOS Why use DSP BIOS Why use DSP BIOS DSP BIOS Configuration Tool DSP BIOS Configuration Tool file file cdb cdb System Setup Tools System Setup Tools Hand...

Page 200: ... the act of a higher priority thread interrupting a lower priority thread interrupting a lower priority thread post post an event signal that often makes a an event signal that often makes a thread ready thread ready pend pend When a thread waits for an event post When a thread waits for an event post semaphore semaphore a data object that tracks event a data object that tracks event occurrences u...

Page 201: ...le solutions Function 1 Function 2 Possible Solution Using while Loop Possible Solution Using while Loop Function 2 Function 1 Main while 1 Potential Problems What if Algorithms run at different rates motor current loop at 20 kHz respond to keypad input at 2 Hz What if one algorithm consumes enough MIPS to force the other algorithm to miss its real time deadlines delays its response Call each func...

Page 202: ...wn ISR running idle Time 1 2 3 5 4 6 7 0 Function 1 Function 2 DSP BIOS Solution DSP BIOS Solution HWI HWI Use DSP BIOS HWI dispatcher for context save restore and allow preemption Reasonable approach if you have limited number of interrupts functions Limitation number of HWI and their priorities are statically determined only one HWI function for each interrupt running idle Time 1 2 3 5 4 6 7 0 N...

Page 203: ...en you configure the interrupt vector in the DSP BIOS config tools Using Software Interrupts Using Software Interrupts SWI SWI main return to O S DSP BIOS Make each algorithm an independent software interrupt SWI scheduling is handled by DSP BIOS HWI function triggered by hardware SWI function triggered by software e g a call to SWI_post Why use a SWI No limitation on number of SWIs and priorities...

Page 204: ...Managing SWI Priority Managing SWI Priority Drag and Drop SWIs to change priority Equal priority SWIs run in the order that they are posted Drag and Drop SWIs to change priority Equal priority SWIs run in the order that they are posted 9 8 C28x Using DSP BIOS ...

Page 205: ...post swi2 Another Solution Another Solution Tasks TSK Tasks TSK DSP BIOS tasks TSK are similar to SWI but offer additional flexibility SWIs must run to completion TSKs can be terminated by software Tradeoffs SWI context switch is faster than TSK TSK module requires more code space TSKs have their own stack User preference and system needs usually dictates choice easy to use both main return to O S...

Page 206: ... DSP BIOS Thread Types DSP BIOS Thread Types Priority Use SWI to perform HWI follow up activity SWI s are posted by software Multiple SWIs at each of 15 priority levels Use TSK to run different programs concurrently under separate contexts TSK s enabled by posting semaphore a signal Multiple IDL functions Runs as an infinite loop like traditional while loop All BIOS data transfers to host occur he...

Page 207: ...urn from main main return to BIOS DSP BIOS Function 2 Function 1 Must delete the endless while loop main returns to BIOS IDLE thread allowing BIOS to schedule events transfer info to host etc An endless while loop in main will not allow BIOS to activate C28x Using DSP BIOS 9 11 ...

Page 208: ...nk requires 0 5 Hz Use the CLK Manager to specify the DSP BIOS CLK rate in microseconds per tick Use the PRD Manager to specify the period for the function in ticks Allows multiple periodic functions with different rates DSP BIOS CLK tick Creating a Periodic Function Creating a Periodic Function period func1 func1 func1 DSP BIOS CLK tick 9 12 C28x Using DSP BIOS ...

Page 209: ...ph Shows amount of CPU horsepower being consumed CPU Load Graph Software logic analyzer Debug event timing and priority Built Built in Real in Real Time Analysis Tools Time Analysis Tools Profile routines w o halting the CPU Statistics View Send debug msgs to host Doesn t halt the DSP Deterministic low DSP cycle count More efficient than traditional printf Message LOG LOG_ LOG_printf printf trace ...

Page 210: ...r Data pipe manager HST HST Host input output manager Host input output manager SIO SIO Stream I O manager Stream I O manager DEV DEV Device driver interface Device driver interface Memory and Low Memory and Low Level Primitives Level Primitives MEM MEM Memory manager Memory manager SYS SYS System services manager System services manager QUE QUE Queue manager Queue manager ATM ATM Atomic functions...

Page 211: ...gers ADC SOC every 20 µs 50 kHz connector wire Compare 1 PWM Circuits Output Logic GP Timer 1 Event Manager ADCINA0 data memory pointer rewind Display Display using CCS using CCS IQmath IQmath FIR Filter FIR Filter Procedure Project File Note LAB9 files have been provided as a starting point for the lab and need to be completed DO NOT copy files from a previous lab 1 A project named Lab9 pjt has b...

Page 212: ...tions the PIE group acknowledge code is left in the HWI rather than move it to a SWI This allows other interrupts to occur on that PIE group even if the SWI has not yet executed On the other hand we are leaving the GPIO and LED toggle code in the HWI just as an example It illustrates that you can post a SWI and also do additional operations in the HWI DSP BIOS is extremely flexible 4 In the beginn...

Page 213: ...ntiate the AdcSwi function itself which is nothing but an ordinary C function from the DSP BIOS SWI object which we are calling ADC_swi 11 Select the Properties for ADC_swi and type _AdcSwi with a leading underscore in the function field Click OK This tells DSP BIOS that it should run the function AdcSwi when it executes the ADC_swi SWI 12 We need to have the PIE for the ADC interrupt use the disp...

Page 214: ...play Type Dual Time Start Address upper display AdcBufFiltered Start Address lower display AdcBuf Acquisition Buffer Size 50 Display Data Size 50 DSP Data Type 32 bit signed integer Q value 24 Sampling Rate Hz 50000 Time Display Unit µs Select OK to save the graph options 18 The graphical display should show the generated IQmath FIR filtered 2 kHz 25 duty cycle symmetric PWM waveform in the upper ...

Page 215: ...riment with different period tick values and notice that the blink rate changes DSP BIOS Real time Analysis The DSP BIOS analysis tools complement the CCS environment by enabling real time program analysis of a DSP BIOS application You can visually monitor a DSP application as it runs with essentially no impact on the application s real time performance In CCS the DSP BIOS analysis tools are found...

Page 216: ...code to the CCS display Unlike an ordinary C language printf which can consume several hundred DSP cycles to format the data on the DSP before transmission to the CCS host PC a log_printf transmits the raw data to the host The host then formats the data and displays it in CCS This consumes only 10 s of cycles rather than 100 s of cycles Add the following to Main_9 c just after the static local var...

Page 217: ...n of the various windows that are open and the information that they are conveying in real time Note In this module only the basic features of DSP BIOS and the real time analysis tools have been used For more information and details please refer to the DSP BIOS user s manuals and other DSP BIOS related training End of Exercise C28x Using DSP BIOS 9 21 ...

Page 218: ...Lab 9 DSP BIOS 9 22 C28x Using DSP BIOS ...

Page 219: ...ogramming and the Code Security Module will be described Learning Objectives Learning Objectives Learning Objectives Emulation and Analysis Block Emulation and Analysis Block External Interface XINTF External Interface XINTF Flash Configuration and Flash Configuration and Memory Performance Memory Performance Flash Programming Flash Programming Code Security Module CSM Code Security Module CSM C28...

Page 220: ...1 Module Topics 10 2 Emulation and Analysis Block 10 3 External Interface XINTF 10 7 Flash Configuration and Memory Performance 10 10 Flash Programming 10 13 Code Security Module CSM 10 15 Lab 10 Programming the Flash 10 19 10 2 C28x System Design ...

Page 221: ...the board H H E E A A D D E E R R System Under Test System Under Test SCAN IN SCAN IN SCAN OUT SCAN OUT Emulator Pod Connections Between Emulator and Connections Between Emulator and Target Target EMU0 EMU0 EMU1 EMU1 TRST TRST TMS TMS TDI TDI TDO TDO TCK TCK EMU0 EMU0 EMU1 EMU1 TRST TRST TMS TMS TDI TDI TDO TDO TCK TCK TCK_RET TCK_RET 13 13 14 14 2 2 1 1 3 3 7 7 11 11 9 9 GND GND PD PD Vcc Vcc GND...

Page 222: ...f the following advanced debug features Halt program execution after a Halt program execution after a specific value is written to a variable specific value is written to a variable 1 Address Watchpoint with Data 1 Address Watchpoint with Data Halt on a specified instruction only Halt on a specified instruction only after some other specific routine has after some other specific routine has execut...

Page 223: ... specifying address ranges address ranges Chained Chained breakpoint breakpoint selection selection On On Chip Emulation Analysis Block Chip Emulation Analysis Block Watchpoints Watchpoints Symbolic or Symbolic or numeric address numeric address Mask value for Mask value for specifying specifying address ranges address ranges Bus selection Bus selection Address with Data Address with Data selectio...

Page 224: ...Watchpoint triggers maskable RTOSINT interrupt Watchpoint triggers maskable RTOSINT interrupt Works with DSP BIOS and non Works with DSP BIOS and non DSP BIOS DSP BIOS See TI application report SPRA820 for implementation details See TI application report SPRA820 for implementation details Data Memory Data Memory Monitor for data Monitor for data writes in region near writes in region near the end ...

Page 225: ...0 0D00 0x00 6000 0x00 6000 0x00 7000 0x00 7000 0x00 8000 0x00 8000 0x00 9000 0x00 9000 0x3D 7800 0x3D 7800 0x3D 8000 0x3D 8000 0x3F 8000 0x3F 8000 0x3F A000 0x3F A000 0x3F F000 0x3F F000 0x3F FFC0 0x3F FFC0 0x3F C000 0x3F C000 0x18 0000 0x18 0000 0x10 0000 0x10 0000 0x08 0000 0x08 0000 0x00 4000 0x00 4000 0x00 2000 0x00 2000 Data Program Data Program 128 128 Bit Password Bit Password reserved 0x3D...

Page 226: ... timing separately for Specify read timing and write timing separately for each zone each zone 1 1 0 0 2 2 XTIMING0 XTIMING0 XTIMING1 XTIMING1 XTIMING2 XTIMING2 XTIMING6 XTIMING6 XTIMING7 XTIMING7 XBANK XBANK Lead Active Trail Lead Active Trail 1 1 0 0 2 2 XCLKOUT XCLKOUT XTIMCLK XTIMCLK SYSCLKOUT SYSCLKOUT C28x C28x CPU CPU XINTCNF2 XINTCNF2 XTIMCLK bit XTIMCLK bit XINTCNF2 XINTCNF2 CLKMODE bit C...

Page 227: ... Bank Control Register XINTF Bank Control Register Configuring XINTF with Header Files Configuring XINTF with Header Files XintfRegs XTIMING0 bit XWRLEAD 1 XintfRegs XTIMING0 bit XWRLEAD 1 XintfRegs XTIMING0 bit XWRACTIVE 2 XintfRegs XTIMING0 bit XWRACTIVE 2 XintfRegs XTIMING0 bit XWRTRAIL 0 XintfRegs XTIMING0 bit XWRTRAIL 0 XintfRegs XTIMING0 bit XRDLEAD 1 XintfRegs XTIMING0 bit XRDLEAD 1 XintfRe...

Page 228: ...EWAIT PAGEWAIT reserved 12 11 12 11 FOTPWAIT FOTPWAIT 0x00 0A87 0x00 0A87 OTPWAIT OTPWAIT reserved 15 15 0 0 4 3 4 3 Refer to the F281x datasheet for detailed numbers Refer to the F281x datasheet for detailed numbers For 150 MHz PAGEWAIT 5 RANDWAIT 5 OTPWAIT 8 For 150 MHz PAGEWAIT 5 RANDWAIT 5 OTPWAIT 8 For 135 MHz PAGEWAIT 4 RANDWAIT 4 OTPWAIT 8 For 135 MHz PAGEWAIT 4 RANDWAIT 4 OTPWAIT 8 16 or 3...

Page 229: ...number of cycles to wait during wake up up from standby to active from standby to active Defaults for these registers are often sufficient Defaults for these registers are often sufficient See See TMS320F28x DSP TMS320F28x DSP System Control and Interrupts Reference Guide SPRU078 for mor System Control and Interrupts Reference Guide SPRU078 for more information e information Code Execution Perform...

Page 230: ...nd ease For cost and power savings and ease of of design use internal RAM design use internal RAM for time for time critical constants before adding external memory to your critical constants before adding external memory to your system system Memory Memory 16 16 bit access bit access 32 32 bit access bit access Notes Notes words cycle words cycle words cycle words cycle Internal RAM Internal RAM ...

Page 231: ...mming Basics Flash Programming Basics Sequence of steps for Flash programming Sequence of steps for Flash programming Minimum Minimum Erase Erase size is a sector size is a sector Minimum Minimum Program Program size is a bit size is a bit Important not to lose power during erase step Important not to lose power during erase step If CSM passwords happen to be all zeros the If CSM passwords happen ...

Page 232: ...grammer Data I O programmer Data I O programmer Build your own custom utility Build your own custom utility Use a different ROM bootloader method than SCI Use a different ROM bootloader method than SCI Embed flash programming into your application Embed flash programming into your application Flash API algorithms provided by TI Flash API algorithms provided by TI Available from TI web at www ti co...

Page 233: ... OTP 1K OTP 1K FLASH 128K FLASH 128K reserved 0x00 8000 0x00 8000 0x00 9000 0x00 9000 0x3D 7800 0x3D 7800 0x3D 8000 0x3D 8000 reserved 0x00 A000 0x00 A000 0x3D 7C00 0x3D 7C00 CSM Password CSM Password 128 128 bit user defined password is stored in Flash bit user defined password is stored in Flash 128 128 bit Key Register used to lock and unlock the bit Key Register used to lock and unlock the dev...

Page 234: ...password bit password 0x3F 7FF9 PWL1 user defined 0x3F 7FF9 PWL1 user defined 2 2nd nd word of 128 word of 128 bit password bit password 0x3F 7FFA PWL2 user defined 0x3F 7FFA PWL2 user defined 3 3rd rd word of 128 word of 128 bit password bit password 0x3F 7FFB PWL3 user defined 0x3F 7FFB PWL3 user defined 4 4th th word of 128 word of 128 bit password bit password 0x3F 7FFC PWL4 user defined 0x3F ...

Page 235: ...ords in your code Generally the CSM is unlocked only for debug Generally the CSM is unlocked only for debug Code Composer Studio can do the unlocking Code Composer Studio can do the unlocking CSM Password Match Flow CSM Password Match Flow Flash device Flash device secure after secure after reset or runtime reset or runtime Do dummy read of PWL Do dummy read of PWL 0x3F 7FF8 0x3F 7FF8 0x3F 7FFF 0x...

Page 236: ...e passwords CsmRegs KEY1 PASSWORD0 to the Key registers CsmRegs KEY1 PASSWORD0 to the Key registers CsmRegs KEY2 PASSWORD2 CsmRegs KEY2 PASSWORD2 CsmRegs KEY3 PASSWORD3 CsmRegs KEY3 PASSWORD3 CsmRegs KEY4 PASSWORD4 CsmRegs KEY4 PASSWORD4 CsmRegs KEY5 PASSWORD5 CsmRegs KEY5 PASSWORD5 CsmRegs KEY6 PASSWORD6 CsmRegs KEY6 PASSWORD6 CsmRegs KEY7 PASSWORD7 CsmRegs KEY7 PASSWORD7 asm EDIS asm EDIS asm EA...

Page 237: ...DS PASSWORDS CPU copies result to buffer during ADC ISR ADC RESULT0 GP Timer 2 GP Timer 2 triggers ADC SOC every 20 µs 50 kHz connector wire Compare 1 PWM Circuits Output Logic GP Timer 1 Event Manager ADCINA0 data memory pointer rewind Display Display using CCS using CCS IQmath IQmath FIR Filter FIR Filter Procedure Project File Note LAB10 files have been provided as a starting point for the lab ...

Page 238: ...ich is the address from which the section is accessed at runtime The linker assigns both addresses to the section Most initialized sections can have the same LOAD and RUN address in the flash However some initialized sections need to be loaded to flash but then run from RAM This is required for example if the contents of the section needs to be modified at runtime by the code 2 This step assigns t...

Page 239: ...main The DSP BIOS configuration tool provides a user initialization function which will be used to perform the trcdata section copy prior to both main and DSP BIOS initialization 5 Open and inspect the file Main_10 c Notice that the function UserInit is used to copy the trcdata section from its load address to its run address before main 6 Open the DSP BIOS configuration file Lab cdb and select th...

Page 240: ...the desired spot in main Code Security Module and Passwords The CSM module provides protection against unwanted copying i e pirating of your code from flash OTP memory and the L0 and L1 RAM blocks The CSM uses a 128 bit password made up of 8 individual 16 bit words They are located in flash at addresses 0x3F7FF8 to 0x3F7FFF During this lab dummy passwords of 0xFFFF will be used therefore only dumm...

Page 241: ...ment initialization routine located in the C compiler runtime support library The entry symbol for this routine is _c_int00 Recall that C code cannot be executed until this setup routine is run Therefore assembly code must be used for the branch We are using the assembly code file named CodeStartBranch asm 17 Open and inspect CodeStartBranch asm This file creates an initialized section named codes...

Page 242: ...area of the plug in window We want to erase all the flash sectors 27 We will not be using the plug in to program the Code Security Password Do not modify the Code Security Password fields 28 In the Operation block notice that the COFF file to Program Verify field automatically defaults to the current out file Check to be sure that Erase Program Verify is selected We will be using the default wait ...

Page 243: ...point succesfully it confirms that the flash has been programmed properly and that the bootloader is properly configured for jump to flash mode and that the codestart section has been linked to the proper address 36 You can now RUN the DSP and you should observe the LED on the board blinking Try resetting the DSP and hitting RUN without doing all the stepping and the Go Main procedure The LED shou...

Page 244: ...Lab 10 Programming the Flash 10 26 C28x System Design ...

Page 245: ...but rather to provide an overview of the features and capabilities Once these features and capabilities are understood additional information can be obtained from various resources such as documentation as needed This module will cover the basic operation of the communication peripherals as well as some basic terms and how they work Learning Objectives Learning Objectives Serial Peripheral Interfa...

Page 246: ...terface SPI 11 4 SPI Registers 11 7 Serial Communications Interface SCI 11 11 Multiprocessor Wake Up Modes 11 14 Multi Channel Buffered Serial Port McBSP 11 17 Enhanced Controller Area Network eCAN 11 20 CAN Bus and Node 11 21 Principles of Operation 11 22 Message Format and Block Diagram 11 23 11 2 C28x Communications ...

Page 247: ... devices Like the GPIO pins they may be used in stand alone or multiprocessing systems In a multiprocessing system they are an excellent choice when both devices have an available serial port and the data rate requirement is relatively low Serial interface is even more desirable when the devices are physically distant from each other because the inherently low number of wires provides a simpler in...

Page 248: ...tly to the SPIDAT register and received data is latched into the SPIBUF register for reading by the CPU This allows for double buffered receive operation in that the CPU need not read the current received data from SPIBUF before a new receive operation can be started However the CPU must read SPIBUF before the new operation is complete of a receiver overrun error will occur In addition double buff...

Page 249: ...r SPIDAT or SPITXBUF 3 Completing Step 2 automatically starts SPICLK signal of the Master 4 MSB of the Master s shift register SPIDAT is shifted out and LSB of the Slave s shift register SPIDAT is loaded 5 Step 4 is repeated until specified number of bits are transmitted 6 SPIDAT register is copied to SPIRXBUF register 7 SPI INT Flag bit is set to 1 8 An interrupt is asserted if SPI INT ENA bit is...

Page 250: ...n 16 bits will be right justified in SPIBUF The non utilized higher significance bits must be masked off by the CPU software when it interprets the character For example a 9 bit character transmission would require masking off the 7 MSB s SPI Data Character Justification Programmable data length of 1 to 16 bits Transmitted data of less than 16 bits must be left justified MSB transmitted first Rece...

Page 251: ... normal operation CLOCK POLARITY 0 rising edge data transfer 1 falling edge data transfer reserved 15 8 3 SPI A Operation Control Register SPICTL 0x007041 0 1 2 15 5 4 3 reserved CLOCK PHASE 0 no CLK delay 1 CLK delayed 1 2 cycle OVERRUN INT ENABLE 0 disabled 1 enabled MASTER SLAVE 0 slave 1 master TALK 0 transmission disabled output pin hi Z d 1 transmission enabled SPI INT ENABLE 0 disabled 1 en...

Page 252: ... to 127 SPI Baud Rate 1 SPIBRR CLKOUT bits sec For SPIBRR 0 1 or 2 SPI Baud Rate 4 CLKOUT bits sec From the above equations one can compute Maximum data rate 37 5 Mbps 150 MHz Character Length Determination The Master and Slave must be configured for the same transmission character length This is done with bits 0 1 2 and 3 of the configuration control register SPICCR 3 0 These four bits produce a ...

Page 253: ... Transmit Register SPIFFTX 0x00704A 0 TXFFIL2 SPIFFEN TXFFST0 TXFFST3 TXFFIEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TXFFIL0 TXFFIL1 TXFFIL4 TXFFIL3 TXFFST1 TXFFINT CLR TXFFST2 TXFFINT TXFFST4 TXFIFO RESET reserved TX FIFO Status read only 00000 TX FIFO empty 00001 TX FIFO has 1 word 00010 TX FIFO has 2 words 00011 TX FIFO has 3 words 10000 TX FIFO has 16 words TX FIFO Interrupt Level Interrupt when ...

Page 254: ...RXFFIL4 0 match RX FIFO Reset 0 reset pointer to 0 1 enable operation RX FIFO Interrupt on match Enable 0 disable 1 enable RX FIFO Interrupt Flag read only 0 not occurred 1 occurred RX FIFO Interrupt Flag Clear 0 no effect 1 clear RX FIFO Overflow Flag read only 0 no overflow 1 overflow RX FIFO Overflow Flag Clear 0 no effect 1 clear SPI Summary Provides synchronous serial communications Two wire ...

Page 255: ...multaneous data transmit and receive Parity checking and data formatting is also designed to be done by the port hardware further reducing software overhead SCI Pin Connections Transmitter data buffer register Transmitter shift register SCI Device 1 SCIRXD SCITXD SCITXD SCIRXD SCI Device 2 8 Receiver data buffer register Receiver shift register 8 Transmitter data buffer register Transmitter shift ...

Page 256: ...Frames are organized into groups called blocks If more than two serial ports exist on the SCI bus a block of data will usually begin with an address frame which specifies the destination port of the data as determined by the user s protocol The start bit is a low bit at the beginning of each frame which marks the beginning of a frame The SCI uses a NRZ Non Return to Zero format which means that in...

Page 257: ... 8 1 2 3 4 5 6 7 8 1 2 Note 8 SCICLK periods per data bit SCI A Baud Rate BAUD15 MSB BAUD14 Baud Select MSbyte Register SCIHBAUD 0x007052 7 6 5 4 3 2 1 0 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 BAUD6 Baud Select LSbyte Register SCILBAUD 0x007053 7 6 5 4 3 2 1 0 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD7 BAUD0 LSB SCI baud rate LSPCLK BRR 1 x 8 LSPCLK 16 BRR 1 to 65535 BRR 0 SCI B Baud Select MSbyte Regis...

Page 258: ...lf the CPU clock rate Multiprocessor Wake Up Modes Multiprocessor Wake Up Modes Allows numerous processors to be hooked up to the bus but transmission occurs between only two of them Idle line or Address bit modes Sequence of Operation 1 Potential receivers set SLEEP 1 which disables RXINT except when an address frame is received 2 All transmissions begin with an address frame 3 Incoming address f...

Page 259: ... bits or greater Address frame follows 10 bit or greater idle 1st data frame SP ST Addr Idle periods of less than 10 bits Address Bit Wake Up Mode All frames contain an extra address bit Receiver wakes up when address bit detected Automatic setting of Addr Data bit in frame by setting TXWAKE 1 prior to writing address to SCITXBUF Last Data ST ST Data SCIRXD SCITXD Block of Frames SP SP Last Data S...

Page 260: ...ing stop bit Each of the above flags can be polled by the CPU to control SCI operations or interrupts associated with the flags can be enabled by setting the RX BK INT ENA SCICTL2 1 and or the TX INT ENA SCICTL2 0 bits active high Additional flag and interrupt capability exists for other receiver errors The RX ERROR flag is the logical OR of the break detect BRKDT framing error FE receiver overrun...

Page 261: ...FIFO_0 DXR1 TX Buffer XSR1 16 RX FIFO_15 RX FIFO_0 DRR2 RX Buffer RBR2 Register 16 RX FIFO_15 RX FIFO_0 DRR1 RX Buffer RBR1 Register 16 RSR2 16 RSR1 DX DR FSX FSR CLKX CLKR Definition Bit and Word CLK b7 b6 b5 b4 b3 b2 b1 b0 Word FS a1 a0 Bit D Word or channel contains number of bits 8 12 16 20 24 32 Bit one data bit per SP clock period C28x Communications 11 17 ...

Page 262: ...c mode R XCER A H Rec Xmt Channel Enable Regs enable disable channels Up to 128 channels can be enabled disabled C O D E C M c B S P Frame TDM Bit Stream Ch0 Ch1 Ch31 0 Ch0 Ch1 Ch31 1 Transmit Receive only selected Channels Multi channel Allows multiple channels words to be independently selected for transmit and receive e g only enable Ch0 5 27 for receive then process via CPU The McBSP keeps tim...

Page 263: ...ommunication Independent clocking and framing for transmit and receive Internal or external clock and frame sync Data size of 8 12 16 20 24 or 32 bits 16 level 32 bit FIFO for transmit data 16 level 32 bit FIFO for receive data TDM mode up to 128 channels SPI mode 75 Mbits sec maximum data rate C28x Communications 11 19 ...

Page 264: ...cking high reliability No node addressing message identifiers Broadcast based signaling C E D A B CAN does not use physical addresses to address stations Each message is sent with an identifier that is recognized by the different nodes The identifier has two functions it is used for message filtering and for message priority The identifier determines if a transmitted message will be received by CA...

Page 265: ...ers 1 Mbps 120Ω 120Ω The DSP communicates to the CAN Bus using a transceiver The CAN bus is a twisted pair wire and the transmission rate depends on the bus length If the bus is less than 40 meters the transmission rate is capable up to 1 Mbit second CAN Node Wired AND Bus Connection RX TX 5V CAN Controller e g TMS320F2812 CAN Transceiver e g TI SN65HVD23x CAN_L CAN_H 120Ω 120Ω C28x Communications...

Page 266: ...t is ignored Unique identifier also determines the priority of the message lower the numerical value of the identifier the higher the priority When two or more nodes attempt to transmit at the same time a non destructive arbitration technique guarantees messages are sent in order of priority and no messages are lost Non Destructive Bitwise Arbitration Bus arbitration resolved via arbitration with ...

Page 267: ... Bytes Data 0 8 Bytes Data CRC CRC ACK ACK r1 r1 18 18 bit bit Identifier Identifier S S R R R R E E O O F F Arbitration Field Data Field The DSP CAN module is a full CAN Controller It contains a message handler for transmission and reception management and frame storage The specification is CAN 2 0B Active that is the module can send and accept standard 11 bit identifier and extended frames 29 bi...

Page 268: ...e frames MDL and MDH contains the data The CAN module contains registers which are divided into five groups These registers are located in data memory from 0x006000 to 0x0061FF The five register groups are Control Status Registers Local Acceptance Masks Message Object Time Stamps Message Object Timeout Mailboxes eCAN Summary Fully CAN protocol compliant version 2 0B Supports data rates up to 1 Mbp...

Page 269: ... the development process Learning Objectives Learning Objectives Learning Objectives Signal Processing Libraries Signal Processing Libraries Additional Resources Additional Resources Internet Internet Product Information Center Product Information Center C28x Development Support 12 1 ...

Page 270: ...Module Topics Module Topics Development Support 12 1 Module Topics 12 2 TI Support Resources 12 3 12 2 C28x Development Support ...

Page 271: ... DSP IQ Math Library DSP IQ Math Library SPRC087 SPRC087 DSP Signal Generator Library DSP Signal Generator Library SPRC083 SPRC083 DSP Software Test Bench STB Library DSP Software Test Bench STB Library SPRC084 SPRC084 C28x Peripheral Examples in C C28x Peripheral Examples in C SPRC097 SPRC097 Available from TI DSP Website Available from TI DSP Website http www dspvillage ti com http www dspvillag...

Page 272: ...erlands English 31 0 546 87 95 45 Spain 34 902 35 40 28 Sweden English 46 0 8587 555 22 United Kingdom 44 0 1604 66 33 99 Finland English 358 0 9 25 17 39 48 Fax All Languages 49 0 8161 80 2045 Email epic ti com Literature Sample Requests and Analog EVM Ordering Information Technical and Design support for all Catalog TI Semiconductor products tools Submit suggestions and errata for tools silicon ...

Page 273: ...Appendix A eZdsp F2812 C28x Appendix A eZdsp F2812 A 1 ...

Page 274: ...m A 3 P2 Expansion Interface A 4 P4 P8 P7 I O Interface A 5 P5 P9 Analog Interface A 7 eZdsp F2812 Jumper Diagram A 8 JP1 XMP MCn Select A 8 JP2 Flash Programming Voltage Select A 8 JP7 JP8 JP11 JP12 Boot Mode Select A 9 JP9 PLL Disable A 9 DS1 DS2 LEDs A 9 TP1 TP2 Test Points A 10 A 2 C28x Appendix A eZdsp F2812 ...

Page 275: ...Appendix eZdsp F2812 eZdsp F2812 Connector Header and Pin Diagram C28x Appendix A eZdsp F2812 A 3 ...

Page 276: ...Appendix P2 Expansion Interface A 4 C28x Appendix A eZdsp F2812 ...

Page 277: ...Appendix P4 P8 P7 I O Interface C28x Appendix A eZdsp F2812 A 5 ...

Page 278: ...Appendix A 6 C28x Appendix A eZdsp F2812 ...

Page 279: ...Appendix P5 P9 Analog Interface C28x Appendix A eZdsp F2812 A 7 ...

Page 280: ...Appendix eZdsp F2812 Jumper Diagram JP1 XMP MCn Select JP2 Flash Programming Voltage Select A 8 C28x Appendix A eZdsp F2812 ...

Page 281: ...Appendix JP7 JP8 JP11 JP12 Boot Mode Select JP9 PLL Disable DS1 DS2 LEDs C28x Appendix A eZdsp F2812 A 9 ...

Page 282: ...Appendix A 10 C28x Appendix A eZdsp F2812 TP1 TP2 Test Points ...

Page 283: ...memory Techniques for managing data pages relevant to direct addressing will be covered as well Finally register addressing allows for interchange between CPU registers Learning Objectives Learning Objectives Learning Objectives Explain sect and Explain sect and usect usect assembly directives assembly directives Explain assembly addressing modes Explain assembly addressing modes Understand instru...

Page 284: ...y Directives B 3 Addressing Modes B 4 Instruction Formats B 5 Register Addressing B 6 Immediate Addressing B 7 Direct Addressing B 8 Indirect Addressing B 10 Review B 13 Exercise B B 14 Lab B Addressing B 15 OPTIONAL Lab B C Array Initialization in C B 17 Solutions B 18 B 2 C28x Appendix B Addressing Modes ...

Page 285: ...to memory or instructions memory or instructions def def start start count count set set 9 9 create an array x of 10 words create an array x of 10 words x x usect usect mydata mydata 10 10 sect sect code code start start C28OBJ C28OBJ operate in C28x mode operate in C28x mode MOV MOV ACC 1 ACC 1 next next MOVL MOVL XAR1 x XAR1 x MOV MOV AR2 count AR2 count loop loop MOV MOV XAR1 AL XAR1 AL BANZ BA...

Page 286: ... mode allows interchange between all CPU registers convenient for solving intricate equations Immediate addressing is helpful for expressing constants easily Direct addressing mode allows information in memory to be accessed Indirect addressing allows pointer support via dedicated auxiliary registers and includes the ability to index or increment through a structure The C28x supports a true softwa...

Page 287: ...gisters from REG loc16 or loc32 for 16 loc16 or loc32 for 16 bit or 32 bit or 32 bit data access bit data access INSTR INSTR REG REG NEG NEG AL AL INSTR INSTR REG REG imm imm MOV MOV ACC 1 ACC 1 INSTR INSTR REG REG mem mem ADD ADD AL x AL x INSTR INSTR mem mem REG REG SUB SUB AL AR0 AL AR0 INSTR INSTR mem mem imm imm MOV MOV XAR0 25 XAR0 25 INSTR INSTR dst dst src src Example Example The C28x foll...

Page 288: ...ters Register addressing allows the exchange of values between registers and with certain instructions can be used in conjunction with other addressing modes yielding a more efficient instruction set Remember that any mem field allows the use of a register as the operand and that no special character such as or need be used to specify the register mode Register Addressing Register Addressing Examp...

Page 289: ...ng allows the user to specify a constant within an instruction mnemonic Short immediate are single word and execute in a single cycle Long 16 bit immediate allow full sized values which become two word instructions yet execute in a single instruction cycle Immediate Addressing Immediate Addressing Example Example Long Immediate 2 Words AND Long Immediate 2 Words AND loc16 loc16 16Bit 16Bit AND AND...

Page 290: ...it DP is concatenated with a 6 bit DP is concatenated with a 6 bit offset from the bit offset from the instruction to generate an absolute 22 instruction to generate an absolute 22 bit address bit address Access data on a given page in any order Access data on a given page in any order 00 0000 0000 0000 00 00 0000 00 0000 0000 0000 00 00 0000 Page 0 00 0000 Page 0 00 0000 00 003F 00 003F 00 0000 0...

Page 291: ...g Direct Addressing Caveats Caveats Z X Y Z X Y x x usect usect samp samp 3 3 sect code sect code ADD ADD AL y AL y MOV MOV z AL z AL Data Memory address address data data 0001C0 0001C0 0001 0001 x x 0001FF 0001FF 1000 1000 y y 000200 000200 0500 0500 Page7 00 Page7 00 Page7 3F Page7 3F Page8 00 Page8 00 MOVW DP x MOVW DP x 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 7 0 0 0 7 0 0 0 0 1 0 0 0 0 0 0 0 1 ...

Page 292: ...ory Auto increment or decrement is supported at no additional cycle cost XAR register formats offer larger 32 bit widths allowing them to access across the full 4 Giga words data space Indirect Addressing Modes Indirect Addressing Modes Auto Auto increment decrement increment decrement XARn XARn XARn XARn Post Post increment or Pre increment or Pre decrement decrement Offset Offset XARn XARn AR0 o...

Page 293: ...hich operates over the base 64K of data memory It offers 6 bit non destructive indexing to access larger stack based arrays efficiently Indirect Addressing Indirect Addressing Example Example Offset Offset x 2 x 1 x 3 x 2 x 1 x 3 MOVL MOVL XAR2 x XAR2 x MOV MOV AR0 1 AR0 1 MOV MOV AR1 3 AR1 3 MOV MOV ACC XAR2 ACC XAR2 AR0 AR0 ADD ADD ACC XAR2 ACC XAR2 AR1 AR1 MOV MOV XAR2 2 AL XAR2 2 AL x x usect ...

Page 294: ... Data Memory Data Memory SP SP x2 x2 x1 x1 x3 x3 0 3 2 0 0 3 2 0 Instr 1 Instr 2 Instr 3 Useful for stack based operations Indirect Addressing Indirect Addressing Example Example Circular Circular AR1 Low is set to buffer size 1 AR1 Low 16 AR1 Low 16 end of buffer start of buffer align on 256 word boundary AAAA AAAA AAAA AAAA SECTIONS Buf_Mem align 256 RAM PAGE 1 LINKER CMD circular buffer range E...

Page 295: ...K 64K Indirect Indirect Addressing Addressing XARn XARn 4G 4G 0x3FFFFF 0x3FFFFF Direct Direct Addressing Addressing DP 16 6 DP 16 6 4M 4M Data memory can be accessed in numerous ways Stack Addressing allows a range to 64K Direct Addressing Offers a 16 bit DP plus a 6 bit offset allowing a 4M range Indirect Addressing Offers the full 4G range C28x Appendix B Addressing Modes B 13 ...

Page 296: ... 30h AL 30h ADD ADD AL XAR1 AL XAR1 MOVW MOVW DP 4006h DP 4006h ADD ADD AL 1 AL 1 SUB SUB AL XAR1 AL XAR1 ADD ADD AL XAR2 AL XAR2 SUB SUB AL XAR2 1 AL XAR2 1 ADD ADD AL 32 AL 32 SUB SUB AL XAR2 2 AL XAR2 2 MOV MOV 32h AL 32h AL Src Src Mode Mode Program Program Imm Imm Immediate Immediate Reg Reg Register Register Dir Direct Dir Direct Idr Idr Indirect Indirect ACC ACC DP DP XAR1 XAR1 XAR2 XAR2 In...

Page 297: ... on the menu bar Select the Linker tab In the middle of the screen select No Autoinitialization under Autoinit Model Create a map file by typing Debug LabB map in the Map Filename m field Enter start in the Code Entry Point e field Next select the Compiler tab Note that Full Symbolic Debug g under Generate Debug Info is selected Then select OK to save the Build Options Initialize Allocated RAM Arr...

Page 298: ...our routine While single stepping it is helpful to see the values located in table 9 and data 9 at the same time Open two memory windows by using the View Memory button on the vertical toolbar and using the address labels table and data Setting the properties filed to Hex TI style will give you more viewable data in the window Additionally it is useful to watch the CPU core and status registers Op...

Page 299: ... the allocated arrays of data 4 coeff 4 and result 1 Note data 9 consists of the allocated arrays of data coeff and result Build and Load 3 Click the Rebuild All button and watch the tools run in the build window Debug as necessary Note Have Code Composer Studio automatically load the output file after a successful build On the menu bar click Option Customize and select the Program Load Options ta...

Page 300: ...XAR2 100180h XAR2 100180h MOV MOV AL 31h AL 31h ADD ADD AL XAR1 AL XAR1 SUB SUB AL 30h AL 30h ADD ADD AL XAR1 AL XAR1 MOVW MOVW DP 4006h DP 4006h ADD ADD AL 1 AL 1 SUB SUB AL XAR1 AL XAR1 ADD ADD AL XAR2 AL XAR2 SUB SUB AL XAR2 1 AL XAR2 1 ADD ADD AL 32 AL 32 SUB SUB AL XAR2 2 AL XAR2 2 MOV MOV 32h AL 32h AL Src Src Mode Mode Program Program 4000 4000 Imm Imm 100100 100100 Imm Imm 100180 100180 Di...

Page 301: ...pick the best instruction for the application Learning Objectives Learning Objectives Perform simple program control using branch and conditional codes Write C28x code to perform basic arithmetic Use the multiplier to implement sum of products equations Use the RPT instruction repeat to optimize loops Use MAC for long sum of products Efficiently transfer the contents of one area of memory to anoth...

Page 302: ...le Math Shift C 7 Multiplier C 9 Basic Multiplier C 10 Repeat Instruction C 11 MAC Instruction C 12 Data Move C 13 Logical Operations C 15 Byte Operations and Addressing C 15 Test and Change Memory Instructions C 16 Min Max Operations C 17 Read Modify Write Operations C 18 Lab C Assembly Programming C 20 OPTIONAL Lab C C Sum of Products in C C 22 C 2 C28x Appendix C Assembly Programming ...

Page 303: ...n fetch mechanism that attempts to keep the pipeline full Branches Branch Types and Range Branch offset 32K 2 word instruction Long Branch absolute 4M 2 word instruction PC Short Branch offset 127 128 1 word instruction Program Memory 0x000000 0x3FFFFF 3 Branch Types The PC can access the entire 4M words 8M bytes range Some branching operations offer 8 and 16 bit relative jumps while long branches...

Page 304: ...2 The assembler will optimize B to SB if possible NEQ EQ GT GEQ LT LEQ HI HIS C LO NC LOS NOV OV NTC TC UNC NBIO Condition Code Instruction Cycles T F Size Condition flags are set on the prior use of the ALU Program Control Call Return Function Call Code Call LCR 22bit 4 LRETR 4 Dynamic Call LCR XARn 4 LRETR 4 Interrupt Return IRET 8 Cycles Return code Cycles More Call variations in the user guide...

Page 305: ... ADD AL XAR2 BANZ BANZ sum AR3 sum AR3 MOV 0 y AL MOV 0 y AL AR3 AR3 COUNT COUNT Data Data x0 x0 x1 x1 x2 x2 x3 x3 x4 x4 x x y y XAR2 XAR2 4 0 n n x y Auxliary Auxliary register used as loop counter register used as loop counter Branch if Branch if Auxilary Auxilary Register not zero Register not zero Test performed on lower 16 Test performed on lower 16 bits of bits of XARx XARx only only C28x Ap...

Page 306: ... the ALU also has the zero cycle barrel shifter and the Accumulator The enhancement that the C28x has is the additional data paths added form the ALU to all internal CPU registers and data memory The connection to all internal registers helps the compiler to generate efficient C code The data path to memory allows the C28x performs single atomic instructions read modify write to the memory The fol...

Page 307: ...ructions with shift option One word instruction no shift ADD ACC 01234h 4 ADDB AL 34h ACC Operations MOV ACC loc16 shift ADD SUB from memory left shift optional MOV ACC 16b shift ADD SUB 16 bit constant left shift optional MOV loc16 ACC shift AL MOVH loc16 ACC shift AH Format Ex Variation Shift the Accumulator Shift full ACC LSL ACC shift SFR ACC shift LSL ACC T SFR ACC T ACC 31 0 SFR ACC 31 0 LSL...

Page 308: ...0 0 C Examples LSLL ACC T LSRL ACC T ASRL ACC T ACC 31 0 C 0 or 1 ACC 31 0 C 0 Note T 4 0 are used other bits are ignored based on SXM Logical Shift Left Long LSLL Logical Shift Right Long LSRL Arithmetic Shift Right Long ASRL C 8 C28x Appendix C Assembly Programming ...

Page 309: ... traditional 16 bit by 16 bit multiplier as previous TI DSP families In addition the C28x has a single cycle 32 bit by 32 bit multiplier to perform extended precision math operations The large multiplier allows the C28x to support higher performance control systems requirement while maintaining small or reduce code The following slides introduce instructions that use the 16 bit by 16 bit multiplie...

Page 310: ...M to ACC SUB ACC P ACC P Sub nth product PM fr ACC Instruction MPYA P T 16b ACC P PM then P T 16b MPYA P T loc16 ACC P PM then P T loc16 MPYS P T loc16 ACC P PM then P T loc16 Execution MOVP T loc16 ACC P PM T loc16 MOVA T loc16 ACC P PM T loc16 MOVS T loc16 ACC P PM T loc16 Sum of Products ZAPA ACC P OVC 0 MOV T X1 T X1 MPY P T A P A X1 MOVA T X2 T X2 ACC A X1 MPY P T B P B X2 MOVA T X3 T X3 ACC ...

Page 311: ... Z3 Z2 Accumulator P register Repeat Instruction Repeat Next RPT Features Next instruction iterated N 1 times Saves code space 1 word Low overhead 1 cycle Easy to use Non interruptible Requires use of before next line May be nested within BANZ loops Options RPT 8bit up to 256 iterations RPT loc16 location loc16 holds count value Instruction Cycles RPT BANZ 1 4 N Example int x 5 0 0 0 0 0 x usect s...

Page 312: ...ro ACC P Zero ACC P Repeat single Repeat single Dual operand Dual operand last ADD last ADD ZAPA ZAPA RPT RPT 19 19 MAC MAC P XAR1 XAR7 P XAR1 XAR7 ADDL ADDL ACC P PM ACC P PM x x usect usect sample 20 sample 20 y y usect usect result 2 result 2 sect coefficient sect coefficient a0 a0 word word 0x0101 0x0101 word word 0x0202 0x0202 word word 0x2020 0x2020 sect code sect code SOP SOP SPM SPM 0 0 MO...

Page 313: ...6 XAR7 PWRITE XAR7 loc16 pointer with a 22 bit program memory address Conditional Moves Instruction Execution if COND is met MOV loc16 AX COND loc16 AX MOVB loc16 8bit COND loc16 8bit If A B Then B A Accumulator 0 0 0 0 0 1 2 0 MOVW DP A MOV AL A CMP AL B Example A usect var 2 1 B set A 1 sect code MOV B AL LT 0 1 2 0 0 3 2 0 Data Memory B A 0 1 2 0 Data Memory B A 0 1 2 0 Before After Instruction...

Page 314: ...on it will execute regardless if the condition is true or not This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Flags and Modes N If the condition is true then after the move AX is tested for a negative condition The nega tive flag bit is set if bit 15 of AX is 1 otherwise it is cleared Z If the condition the...

Page 315: ...ow byte for register addressing 2 Low byte for direct addressing 3 Selected byte for offset indirect addressing Byte Addressing MOVL XAR2 MemA MOVB XAR2 1 AL LSB MOVB XAR2 2 AL MSB MOVB XAR2 5 AH LSB MOVB XAR2 6 AH MSB AR2 AH MSB AH LSB AL MSB AL LSB 16 bit memory 01 02 05 06 12 34 56 78 04 07 00 03 34 56 12 78 MOVL XAR2 MemA MOVB AL LSB XAR2 1 MOVB AL MSB XAR2 2 MOVB AH LSB XAR2 4 MOVB AH MSB XAR...

Page 316: ...it to be extracted to the test control TC field of status register 0 The contents of the accumulator can also be non destructively analyzed to establish branching conditions as seen below Test and Change Memory Instruction Execution Affects TBIT loc16 0 15 ST0 TC loc16 bit_no TC TSET loc16 0 15 Test loc16 bit then set bit TC TCLR loc16 0 15 Test loc16 bit then clr bit TC CMPB AX 8bit Test AX 8bit ...

Page 317: ...16 ACC loc16 if ACC loc16 do nothing MIN ACC loc16 if ACC loc16 ACC loc16 if ACC loc16 do nothing MAXL ACC loc32 if ACC loc32 ACC loc32 if ACC loc32 do nothing MINL ACC loc32 if ACC loc32 ACC loc32 if ACC loc32 do nothing MAXCUL P loc32 if P loc32 P loc32 for 64 bit math if P loc32 do nothing MINCUL P loc32 if P loc32 P loc32 for 64 bit math if P loc32 do nothing C28x Appendix C Assembly Programmi...

Page 318: ...iplication operation These one or two cycle operations are referred to as read modify write operations or as atomic instructions Read Modify Write Instructions AND loc16 16b OR loc16 16b XOR loc16 16b ADD loc16 16b SUBR loc16 16b AND loc16 AX OR loc16 AX XOR loc16 AX ADD loc16 AX SUB loc16 AX SUBR loc16 AX INC loc16 DEC loc16 TSET loc16 bit TCLR loc16 bit AH AL 16 bit constant Work directly on mem...

Page 319: ...TM MOV AL VarB ADD AL VarA MOV VarA AL CLRC INTM SETC INTM MOV AL VarA ADD AL 100 MOV VarA AL CLRC INTM SETC INTM MOV AL VarA ADD AL 1 MOV VarA AL CLRC INTM update with a mem update with a constant update by 1 Benefits of Read Benefits of Read Modify Modify Write Instructions Write Instructions C28x Appendix C Assembly Programming C 19 ...

Page 320: ...ject File 1 Create a new project called LabC pjt in C C28x Labs Appendix LabC and add LabC asm and LabC cmd to it Check your file list to make sure all the files are there Be sure to setup the Build Options by clicking Project Build Options on the menu bar Select the Linker tab In the middle of the screen select No Autoinitialization under Autoinit Model Create a map file by typing Debug LabC map ...

Page 321: ...rogram If you wish right click on the source window and select Mixed Mode to debug using both source and assembly 7 Single step your routine While single stepping open memory windows to see the values located in table 9 and data 9 Open the CPU Registers Check to see if the program is working as expected Debug and modify if needed Optional Exercise After completing the above edit LabC asm and modif...

Page 322: ...roducts using a MAC based Implementation 2 Edit LabC C c and modify the main routine to perform a MAC based implementation in C Since the MAC operation requires one array to be in program memory the initialization routine can skip the transfer of one of the arrays thus reducing the amount of data RAM and cycles required for initialization Build and Load 3 Click the Rebuild All button and watch the...

Page 323: ...d Also the C compiler optimization features will be explained Learning Objectives Learning Objectives Learning Objectives Learn the basic C environment for Learn the basic C environment for the C28x family the C28x family How to control the C environment How to control the C environment How to use the C How to use the C compiler optimizer compiler optimizer Discuss the importance of volatile Discu...

Page 324: ...Stack D 4 C28x Data Types D 5 Accessing Interrupts Status Register D 6 Using Embedded Assembly D 7 Using Pragma D 8 Optimization Levels D 9 Volatile Usage D 11 Compiler Advanced Options D 12 Optimization Tips Summary D 13 Lab D C Optimization D 14 OPTIONAL Lab D2 C Callable Assembly D 17 Solutions D 20 D 2 C28x C Programming ...

Page 325: ...eset vector should contain a long to this address to make boot asm the reset routine The contents of the boot routine have been extracted and copied on the following page so they may be inspected Note the various functions performed by the boot routine including the allocation and setup of the stack setting of various C requisite statuses the initialization of global and static variables and the c...

Page 326: ...g Up the Stack Boot Boot asm asm sets up SP to sets up SP to point at stack point at stack The stack section has to The stack section has to be linked into the low 64k be linked into the low 64k of data memory The SP is of data memory The SP is a 16 a 16 bit register and cannot bit register and cannot access addresses beyond access addresses beyond 64K 64K Stack size is set by the Stack size is se...

Page 327: ...larger or larger 32 32 2M 2M 32 bits signed 2M 2M 32 bits signed unsigned long unsigned long 32 32 0 4M 32 bits unsigned 0 4M 32 bits unsigned float float 32 32 IEEE single precision IEEE single precision double double 64 64 IEEE double precision IEEE double precision long double long double 64 64 IEEE double precision IEEE double precision Data which is 32 Data which is 32 bits wide such as longs...

Page 328: ...d bits clear desired bits IER Mask IER Mask set desired bits set desired bits IFR 0x0000 IFR 0x0000 clear prior interrupts clear prior interrupts Interrupt Enable Interrupt Flag Registers IER IFR are not Interrupt Enable Interrupt Flag Registers IER IFR are not memory mapped memory mapped Only limited instructions can access IER IFR more in interrup Only limited instructions can access IER IFR mor...

Page 329: ...uld be written in ASM and called from C main C file retains portability main C file retains portability yields more easily maintained structures yields more easily maintained structures eliminates risk of interfering with registers in use by C eliminates risk of interfering with registers in use by C define EINT define EINT asm asm CLRC INTM CLRC INTM The assembly function allows for C files to co...

Page 330: ... identified otherwise by using the code section pragma like sect in assembly pragma pragma CODE_SECTION CODE_SECTION func func section name section name pragma pragma DATA_SECTION symbol section name DATA_SECTION symbol section name User defined sections from C User defined sections from C Pragma Pragma Examples Examples global _ global _bufferA bufferA _ _bufferB bufferB bss bss _bufferA 512 _buf...

Page 331: ...sed to invoke the optimizations It is recommended that optimization be invoked in steps and that code be verified before advancing to the next step Intermediate steps offer the gradual transition from fully sym bolic to fully optimized compilation Compiler switched may be invoked in a variety of ways Here are 4 steps that could be considered 1st use g By starting out with g you do no optimization ...

Page 332: ...ions declared inline o1 o1 Performs local copy constant propagation Performs local copy constant propagation Removes unused assignments Removes unused assignments Eliminates local common expressions Eliminates local common expressions o2 o2 Default Default o o Performs loop optimizations Performs loop optimizations Eliminates global common sub Eliminates global common sub expressions expressions E...

Page 333: ... of existence Hence it may be eliminated optimized out of existence CTRL CTRL 1 1 No No Yes Yes Optimizer removes Optimizer removes empty loop empty loop empty empty loop loop When using optimization it is important to declare variables as When using optimization it is important to declare variables as volatile volatile when when The memory location may be The memory location may be modifed modife...

Page 334: ...ptimization Note Some symbolic debug labels will be lost when mn option is used Optimizer should be invoked incrementally g test Symbols kept for debug g o3 test Add optimizer keep symbols g o3 mn test More optimize some symbols o3 test Final rev Full optimize no symbols mf Optimize for speed instead of the default optimization for code size mi Avoid RPT instruction Prevent compiler from generatin...

Page 335: ...tween files static inlines inlines in header files in header files Invoke automatic Invoke automatic inlining inlining o3 o3 oi oi Give compiler project visibility use Give compiler project visibility use pm and pm and o3 o3 Tune memory map via linker command file Tune memory map via linker command file Re Re write key code segments to use intrinsics or in assembly write key code segments to use i...

Page 336: ...piler tab Note that Full Symbolic Debug g under Generate Debug Info in the Basic Category is selected On the Feedback Category pull down the interlisting options and select C and ASM ss On the Assembly Category check the Keep generated asm Files k Keep Labels as Symbols as and Generate Assembly Listing Files al The as will allow you to see symbols in the memory window and the al will generate an a...

Page 337: ...should be stopped at the first breakpoint in sop Double click on the clock window to set the clock to zero Now you are ready to benchmark the code Run to the second breakpoint The number of cycles are displayed in the clock window Record this value in the table at the end of the lab under C Code Cycles C Optimization 12 To optimize C code to the highest level we must set up new Build Options for o...

Page 338: ... reset it Run to the last breakpoint Record the number of cycles the assembly code ran 18 How does assembly C code and oprimized C code compare on the C28x C Code Optimized C Code o3 Assembly Code Code Size Cycles End of Exercise D 16 C28x C Programming ...

Page 339: ...er Autoinit Model Create a map file by typing Debug LabD2 map in the Map Filename m field Do not enter anything in the Code Entry Point e field leave it blank Set the stack size to 0x400 Next select the Compiler tab Note that Full Symbolic Debug g under Generate Debug Info in the Basic Category is selected On the Feedback Category pull down the interlisting options and select C and ASM ss On the A...

Page 340: ... on the left most button on the horizontal toolbar New and save it as an assembly source file with the name sop asm asm Next copy ONLY the sum of products function from LabC asm into this file Add a _sop label to the function and make it visible to the linker def Also be sure to add a sect directive to place this code in the code section Finally add the following instruction to the end LRETR retur...

Page 341: ...ated with that name from the original LabD2 c code Defining the Function Prototype as External 14 Note in LabD2 c an extern modifier is placed in front of the sum of products function prototype extern int sop int int int sop function prototype Verify Assembly Sum of Products Routine 15 Remove the sop c c file from the project and add the new sop asm asm assembly file to the project 16 Rebuild and ...

Page 342: ... C28x C Programming Solutions Lab D Solutions Lab D Solutions 22 22 32 32 118 118 Cycles Cycles 11 11 12 12 27 27 Code Size Code Size Assembly Assembly Code Code Optimized Optimized C Code C Code o3 o3 C Code C Code ...

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