Texas Instruments C28 Series, Student Manual

Page: 12 / 342

C28x CPU
Pipeline Advantage
F F
1
1
F F
2
2
D D
1
1
D D
2
2
R R
1
1
R R
2
2
X X
C28x Pipeline
C28x Pipeline
Protected Pipeline
Protected Pipeline
¾ ¾
Order of results are as written in
Order of results are as written in
source code
source code
¾ ¾
Programmer need not worry about
Programmer need not worry about
the pipeline
the pipeline
8
8
-
-
stage pipeline
stage pipeline
F
F
1 1
F
F
2 2
D
D
1 1
D
D
2 2
R
R
1 1
R
R
2 2
X
X
F
F
1 1
F
F
2 2
D
D
1 1
D
D
2 2
R
R
1 1
R
R
2 2
X
X
F F
1 1
F F
2 2
D D
1 1
D D
2 2
R R
1 1
R R
2 2
X X
F F
1 1
F F
2 2
D D
1 1
D D
2 2
R R
1 1
R R
2 2
X X
F F
1
1
F F
2
2
D D
1
1
D D
2
2
R R
1
1
R R
2
2
X X
F F
1
1
F F
2
2
D D
1
1
D D
2
2
R R
1
1
R R
2
2
X X
F F
1 1
F F
2 2
D D
1 1
D D
2 2
R R
1 1
R R
2 2
X X
A A
B B
C
C
D D
E E
F
F
G
G
W
W
W
W
W
W
W
W
W W
W W
W
W
W W
E & G Access
E & G Access
same address
same address
R
R
1
1
R
R
2
2
X
X
W
W
D D
2
2
R R
1
1
R R
2
2
X W X W
F1: Instruction Address
F1: Instruction Address
F2: Instruction Content
F2: Instruction Content
D1: Decode Instruction D1: Decode Instruction
D2: Resolve Operand Addr
D2: Resolve Operand Addr
R1: Operand Address
R1: Operand Address
R2: Get Operand
R2: Get Operand
X: CPU doing “real” work X: CPU doing “real” work
W: store content to memory W: store content to memory
H H
The C28x uses a special 8-stage protected pipeline to maximize the throughput. This protected
pipeline prevents a write to and a read from the same location from occurring out of order.
This pipelining also enables the C28x to execute at high speeds without resorting to expensive
high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional
discontinuities. Special store conditional operations further improve performance.
1 - 8 C28x - Architecture Overview