Oscillator/PLL Clock Module
Oscillator/PLL Clock Module
C28x Oscillator / PLL Clock Module
C28x Oscillator / PLL Clock Module
PLLCR @ 0x007021
PLLCR @ 0x007021
(lab file:
(lab file:
SysCtrl
SysCtrl
.c)
.c)
DIV3 DIV2 DIV1 DIV0
DIV3 DIV2 DIV1 DIV0
Clock Frequency (CLKIN)
Clock Frequency (CLKIN)
0 0 0 0
0 0 0 0
OSCCLK x 1 / 2 (no PLL) *
OSCCLK x 1 / 2 (no PLL) *
0 0 0 1
0 0 0 1
OSCCLK x 1 / 2
OSCCLK x 1 / 2
0 0 1 0
0 0 1 0
OSCCLK x 2 / 2
OSCCLK x 2 / 2
0 0 1 1
0 0 1 1
OSCCLK x 3 / 2
OSCCLK x 3 / 2
0 1 0 0
0 1 0 0
OSCCLK x 4 / 2
OSCCLK x 4 / 2
0 1 0 1
0 1 0 1
OSCCLK x 5 / 2
OSCCLK x 5 / 2
0 1 1 0
0 1 1 0
OSCCLK x 6 / 2
OSCCLK x 6 / 2
0 1 1 1
0 1 1 1
OSCCLK x 7 / 2
OSCCLK x 7 / 2
1 0 0 0
1 0 0 0
OSCCLK x 8 / 2
OSCCLK x 8 / 2
1 0 0 1
1 0 0 1
OSCCLK x 9 / 2
OSCCLK x 9 / 2
1 0 1 0
1 0 1 0
OSCCLK x 10 / 2
OSCCLK x 10 / 2
PLLCR
PLLCR
bits 15:4
bits 15:4
reserved
reserved
crystal
crystal
PLL
PLL
Clock Module
Clock Module
4
4
-
-
bit PLL Select
bit PLL Select
X1 /CLKIN
X1 /CLKIN
X2
X2
XT
A
L
O
SC
XT
AL O
SC
Watchdog
Watchdog
Module
Module
/2
/2
PLLCLK
PLLCLK
OSCCLK
OSCCLK
•
•
C28x
C28x
Core
Core
CLKIN
CLKIN
MUX
MUX
XF_XPLLDIS
XF_XPLLDIS
0
0
1
1
SYSCLKOUT
SYSCLKOUT
HISPCP
HISPCP
LOSPCP
LOSPCP
HSPCLK
HSPCLK
LSPCLK
LSPCLK
•
•
•
•
* default
* default
The OSC/PLL clock module provides all the necessary clocking signals for C28x devices. The
PLL has a 4-bit ratio control to select different CPU clock rates. Two modes of operation are
supported – crystal operation, and external clock source operation. Crystal operation allows the
use of an external crystal/resonator to provide the time base to the device. External clock source
operation allows the internal oscillator to be bypassed, and the device clocks are generated from
an external clock source input on the X1/CLKIN pin. The watchdog receives a clock signal from
OSCCLK. The C28x core provides a SYSCLKOUT clock signal. This signal is prescaled to
provide a clock source for the on-chip peripherals through the high-speed and low-speed
peripheral clock prescalers.
C28x - System Initialization
5 - 3
Summary of Contents for C28 Series
Page 64: ...Summary 3 16 C28x Peripheral Registers Header Files ...
Page 78: ...Interrupt Sources 4 14 C28x Reset and Interrupts ...
Page 218: ...Lab 9 DSP BIOS 9 22 C28x Using DSP BIOS ...
Page 244: ...Lab 10 Programming the Flash 10 26 C28x System Design ...
Page 273: ...Appendix A eZdsp F2812 C28x Appendix A eZdsp F2812 A 1 ...
Page 276: ...Appendix P2 Expansion Interface A 4 C28x Appendix A eZdsp F2812 ...
Page 277: ...Appendix P4 P8 P7 I O Interface C28x Appendix A eZdsp F2812 A 5 ...
Page 278: ...Appendix A 6 C28x Appendix A eZdsp F2812 ...
Page 279: ...Appendix P5 P9 Analog Interface C28x Appendix A eZdsp F2812 A 7 ...
Page 282: ...Appendix A 10 C28x Appendix A eZdsp F2812 TP1 TP2 Test Points ...