Table 16-2. Startup Sequence and Timing
Step
Comment
FASTADC Setting
Time (relative to wakeup event)
Wakeup event
Either the TS2 pin is pulled
low, or the LD pin is pulled
up, triggering the device to exit
SHUTDOWN mode.
0, 1
0
REG1 powered
This was measured with the OTP
programmed to autonomously
power the REG1 LDO.
0, 1
20 ms
INITSTART asserted
This was measured with the
OTP programmed to provide the
INITSTART bit in the Alarm signal
on the ALERT pin.
0, 1
22 ms
INITCOMP and ADSCAN
asserted
This was measured with the
OTP programmed to provide the
INITCOMP and ADSCAN bits in
the Alarm signal on the ALERT
pin.
0
69 ms
1
47 ms
FULLSCAN asserted
This was measured with the
OTP programmed to provide the
FULLSCAN bit in the Alarm
signal on the ALERT pin.
0
164 ms
1
97 ms
FETs enabled
This was measured with the OTP
programmed to autonomously
enable FETs.
0
282 ms
1
283 ms
shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP
with
[FASTADC]
= 1,
[FET_EN]
= 1 for autonomous FET control, setup to use three thermistors, and providing
the
[INITCOMP]
flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN.
Figure 16-5. Startup Sequence Using [FASTADC] = 1, with the [INITCOMP] Flag Displayed on the ALERT
Pin.
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
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