16.3 Random Cell Connection Support
The BQ76942 device supports a random connection sequence of cells to the device during pack manufacturing.
For example, cell 7 in a 10-cell stack might be first connected at the input terminals leading to pins VC7 and
VC6, then cell 4 may next be connected at the input terminals leading to pins VC4 and VC3, and so on. It
is not necessary to connect the negative terminal of cell 1 first at VC0. As another example, consider a cell
stack that is already assembled and cells already interconnected to each other, then the stack is connected to
the PCB through a connector plugged in or soldered to the PCB. In this case, the sequence order in which
the connections are made to the PCB can be random in time; they do not need to be controlled in a certain
sequence.
There are, however, some restrictions to how the cells are connected during manufacturing:
• IMPORTANT: The cells in a stack
cannot
be connected to
any
VC pin on the device randomly, such as
the lowest cell (cell 1) connected to VC9, while the top cell (cell 10) is connected to VC4, and so on. It
is important that the cells in the stack be connected in ascending pin order, with the lowest cell (cell 1)
connected between VC1 and VC0, the next higher voltage cell (cell 2) connected between VC2 and VC1, and
so on.
• The random cell connection support is possible due to high voltage tolerance on pins VC1–VC10.
Note
VC0 has a lower voltage tolerance. This is because VC0 should be connected through the series-
cell input resistor to the VSS pin on the PCB, before any cells are attached to the PCB. Thus, the
VC0 pin voltage is expected to remain close to the VSS pin voltage during cell attach. If VC0 is
not connected through the series resistor to VSS on the PCB, then cells cannot be connected in
random sequence.
• Each of the VC1–VC10 pins includes a diode between the pin and the adjacent lower cell input pin (that is,
between VC10 and VC9, between VC9 and VC8, and so on), which is reverse-biased in normal operation.
This means an upper cell input pin should not be driven to a low voltage while a lower cell input pin is driven
to a higher voltage, since this would forward bias these diodes. During cell attach, the cell input terminals
should generally be floating before they are connected to the appropriate cell. It is expected that transient
current will flow briefly when each cell is attached, but the cell voltages quickly stabilize to a state without DC
current flowing through the diodes. However, if a large capacitance is included between a cell input pin and
another terminal (such as VSS or another cell input pin), the transient current may become excessive and
lead to device heating. Therefore, it is recommended to limit capacitances applied at each cell input pin to the
values recommended in the specifications.
16.4 Startup Timing
At initial power up of the BQ76942 from a SHUTDOWN state, the device will progress through a sequence of
events before entering NORMAL mode operation. These are described below for an example configuration, with
approximate timing shown for the cases when
[FASTADC]
= 0 and
[FASTADC]
= 1.
Note
When the device is configured for autonomous FET control (that is,
[FET_EN]
= 1), the decision to
enable FETs is only evaluated every 250 ms while in NORMAL mode, which is why the FETs are
not enabled until approximately 280 ms after the wakeup event, even though the data was available
earlier.
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
70
Copyright © 2021 Texas Instruments Incorporated
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