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PACK-

VDD

GPIO

INT

3.3V

COMM

COMM TO

SYSTEM

GPIO

SDA

SCL

FUSE

CHG Logic Out

SECONDARY

PROTECTOR

VC5

VC4

VC7

VC6

VC8

VC9

BRE

PCHG

PDSG

FUSE

C10

CHG

DSG

CP1

G18

SRP

SRN

SDA

REG1

RST_SHUT

DDSG

DCHG

DFETOFF

SCL

REG2

CFETOFF

HDQ

REGIN

ALERT

PACK+

PDSG

PCHG

FUSE

PDSG

PCHG

DSG Logic Out

GND

MCU

COMMUNICATIONS

TRANSCEIVER

Figure 16-1. BQ76942 10-Series Cell Typical Implementation (Simplified Schematic)

16.2.1 Design Requirements (Example)

Table 16-1. BQ76942 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

Minimum system operating voltage

25 V

Cell minimum operating voltage

2.5 V

Series cell count

Sense resistor

1 mΩ

Number of thermistors

3 (using TS1, TS2, and TS3 pins, all for cells)

Charge voltage

42.5 V

Maximum charge current

8.0 A

Peak discharge current

20.0 A

Configuration settings

programmed in OTP during customer production

Protection subsystem configuration

Series FET configuration, device monitors, disables FETs upon fault, recovers autonomously

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BQ76942

SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021

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BQ76942

Summary of Contents for BQ76942

Page 1: ...QFP package PFB 2 Applications Cordless power tools and garden tools Vacuum cleaners E bike e scooter and LEV Non military drones Other industrial battery pack 3 series 10 series 3 Description The Tex...

Page 2: ...r Temperature Measurement 37 10 7 Factory Trim of Voltage ADC 38 10 8 Voltage Calibration ADC Measurements 38 10 9 Voltage Calibration COV and CUV Protections 39 10 10 Current Calibration 40 10 11 Tem...

Page 3: ...chematic Denoted capacitors on sense resistor inputs to VSS as optional 63 Updated Documentation Support 78 Changes from Revision November 2020 to Revision A January 2021 Page Updated Description 1 Up...

Page 4: ...29 CFETOFF 40 PCHG 21 TS1 9 NC 28 HDQ 39 PDSG 22 TS2 10 VC5 27 SDA 38 FUSE 23 TS3 11 NC 26 SCL 37 BREG 24 REG18 12 VC4 25 ALERT Not to scale Figure 6 1 Pinout top Table 6 1 BQ76942 TQFP Package PFB P...

Page 5: ...ird cell from the bottom of the stack 15 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack balance current input for the first cell from the bottom of the stack and retu...

Page 6: ...ogrammed for 1 8 V 2 5 V 3 0 V 3 3 V or 5 0 V 36 REGIN I IA Input pin for REG1 and REG2 LDOs 37 BREG O OA Base control signal for external preregulator transistor 38 FUSE I O I OA Fuse sense and drive...

Page 7: ...ge range VIN TS1 TS2 TS3 ALERT CFETOFF DFETOFF HDQ DCHG DDSG when used as thermistor or general purpose ADC input VSS 0 3 VREG18 0 3 V Input voltage range VIN SRP SRN VSS 0 3 VREG18 0 3 V Input voltag...

Page 8: ...nt allowed to flow into the FUSE pin must be limited such as by using external series resistance to 2 mA or less 3 When the ALERT HDQ CFETOFF DFETOFF DCHG or DDSG pins are selected for thermistor inpu...

Page 9: ...2 0 2 V VIN Input voltage range 3 SRP SRN without measuring current 0 2 0 75 V VIN Input voltage range 3 4 VVC 0 0 2 0 5 V VIN Input voltage range 5 VVC x 1 x 4 maximum of VVC x 1 0 2 or VSS 0 2 mini...

Page 10: ...onal and new thermal metrics see the Semiconductor and IC Package Thermal Metrics application report 7 5 Supply Current Typical values stated where TA 25 C and VBAT 55 0 V min max values stated where...

Page 11: ...FF DCHG DDSG REGIN TS1 TS2 TS3 2 pF ILKG Input leakage current ALERT SCL SDA HDQ CFETOFF DFETOFF DCHG DDSG REGIN device in SHUTDOWN mode 1 A 1 Specified by design 7 7 LD Pin Typical values stated wher...

Page 12: ...oltage 1 6 1 8 2 V VO TEMP Regulator output over temperature VREG18 vs VREG18 at 25 C IREG18 1 mA VBAT 37 0 V 0 15 VO LINE Line regulation VREG18 vs VREG18 at 25 C VBAT 37 0 V IREG18 1 mA as VBAT vari...

Page 13: ...25 C VREGIN 5 5 V IREG1 20 mA as VREGIN varies from 5 V to 6 V VREG1 set to nominal 3 3 V setting 1 1 ISC Regulator short circuit current limit VREG1 0 V 47 80 mA CEXT External capacitor REG1 to VSS 1...

Page 14: ...C_IN Input voltage range for measurements 3 VSRP VSRN 0 2 0 2 V B CC_INL Integral nonlinearity 2 16 bit best fit over input voltage range 5 2 22 3 LSB 1 B CC_DNL Differential nonlinearity 2 16 bit no...

Page 15: ...asured using averaged data to remove effects of noise 200 200 V VWAKE_THR Wakeup voltage threshold error 1 TA 25 C VWAKE VSRP VSRN setting beyond 5 mV Measured using averaged data to remove effects of...

Page 16: ...C 4 R ADC_IN_CELL Effective input resistance 2 Differential cell input mode on VC10 VC9 8 3 0 M R ADC_IN_LD Effective input resistance Divider measurement on LD pin only active while the LD pin is bei...

Page 17: ...V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V TEMP Internal temperature sensor voltage drift VBE measurement 0 410 mV C 7 23 Thermistor Measurement Typical values stated where...

Page 18: ...ation of design and production test 7 25 High Side NFET Drivers Typical values stated where TA 25 C and VBAT 55 0 V min max values stated where TA 40 C to 85 C and VBAT 4 7 V to 55 V unless otherwise...

Page 19: ...ue may be desired to avoid an overly fast FET turn off which can result in a large voltage transient due to cell and harness inductance 7 26 Comparator Based Protection Subsystem Typical values stated...

Page 20: ...rge voltage threshold range Nominal settings threshold based on VSRP VSRN 10 20 40 60 80 100 125 150 175 200 250 300 350 400 450 500 mV V SCD_ACC Short circuit in discharge voltage threshold detection...

Page 21: ...of the SCL clock 1 4 7 s tHIGH High period of the SCL clock 1 4 0 s tSU STA Setup repeated START 1 4 7 s tHD DAT Data hold time SDA input 1 0 ns tSU DAT Data setup time SDA input 1 250 ns tr Clock ris...

Page 22: ...s HDQ 32 50 s tDW0 Device Write 0 Time 1 Device drives HDQ 80 145 s tRSPS Device Response Time 1 3 Device drives HDQ 190 s tTRND Host Turn Around Time 1 Host drives HDQ after device drives HDQ 210 s t...

Page 23: ...es 15 ns setup time on the SPI controller for MISO If additional setup time is required the clock period should be extended accordingly 5 When SPI pin filtering is enabled pulses on input pins of dura...

Page 24: ...address 1 bit R W 7 bit address t RSPS Break d Device Transmitted Bit c HDQ Host Transmitted Bit T HW1 T HW0 T CYCH T DW1 T DW0 T CYCD 1 2 V t B t BR b HDQ Line Rise Time a Break and Break Recovery t...

Page 25: ...with Cell Voltage 2 5 V Figure 7 7 Cell Voltage Measurement Error vs Temperature with Cell Voltage 3 5 V Figure 7 8 Cell Voltage Measurement Error vs Temperature with Cell Voltage 4 5 V Figure 7 9 Ce...

Page 26: ...perature VREF1 and VREF2 Figure 7 12 Internal Temperature Sensor Delta VBE Voltage vs Temperature LFO measured in full speed mode 262 kHz Figure 7 13 Low Frequency Oscillator LFO Accuracy vs Temperatu...

Page 27: ...Threshold vs Temperature Figure 7 16 Overcurrent in Charge Protection OCC Threshold vs Temperature Figure 7 17 Cell Balancing Resistance vs Temperature www ti com BQ76942 SLUSE14B DECEMBER 2020 REVIS...

Page 28: ...re 7 18 Cell Balancing Resistance vs Cell Common Mode Voltage at 25 C Figure 7 19 REG1 Voltage vs Load at 25 C Figure 7 20 REG2 Voltage vs Load at 25 C Figure 7 21 Thermistor Pullup Resistance vs Temp...

Page 29: ...8 1 785 1 79 1 795 1 8 1 805 1 81 1 815 1 82 1 825 1 83 1 835 BAT 4 7V 0mA BAT 8V 0mA BAT 10V 0mA BAT 20V 0mA BAT 25 9V 0mA BAT 40V 0mA BAT 60V 0mA BAT 4 7V 1mA BAT 8V 1mA BAT 10V 1mA BAT 20V 1mA BAT...

Page 30: ...ature Figure 7 30 BAT Current in SLEEP2 SRC Follower Mode vs Temperature Figure 7 31 BAT Current in DEEPSLEEP2 No LFO Mode vs Temperature BQ76942 SLUSE14B DECEMBER 2020 REVISED DECEMBER 2021 www ti co...

Page 31: ...o setup device operation on their own production line Multiple communications interfaces are supported including 400 kHz I2C SPI and HDQ one wire standards Multiple digital control and status data are...

Page 32: ...age references integrated within the device a hardware monitor of the LFO frequency memory checks at power up or reset an internal watchdog on the embedded processor and more These are described in de...

Page 33: ...can be changed Data memory settings cannot be changed directly UNSEALED mode includes SEALED functionality and also adds the ability to execute additional subcommands and read and write data memory FU...

Page 34: ...re thermistors or ADCIN are enabled measurement slots The speed of a measurement loop can be controlled by settings Each voltage measurement slot takes 3 ms or 1 5 ms depending on setting so a typical...

Page 35: ...n in Figure 10 2 for VC8 Figure 10 2 Terminating an Unused Cell Input Pin A configuration register is used to specify which cell inputs are used for actual cells The device uses this information to di...

Page 36: ...red 10 2 General Purpose ADCIN Functionality Several multifunction pins on the BQ76942 device can be used for general purpose ADC input ADCIN measurement if not being used for other purposes This incl...

Page 37: ...igital communication interface while the measurements taken that were synchronized with particular cell voltage measurements are stored paired with the associated cell voltage measurement for separate...

Page 38: ...for gain therefore the customer will need to process them before use The device includes a factory gain trim for the voltage measurements performed using the general purpose ADC input capability on th...

Page 39: ...n Voltage LD Gain 16 bit ADC counts 65536 Calibration Vdiv Offset Vdiv Offset ADCIN Voltage Calibration Voltage ADC Gain 16 bit ADC counts 65536 Note Cell Voltage and Calibration Vcell Offset Vcell Of...

Page 40: ...t 0 1 K Calibration Temperature CFETOFF Temp Offset CFETOFF pin thermistor 0 1 K Calibration Temperature DFETOFF Temp Offset DFETOFF pin thermistor 0 1 K Calibration Temperature ALERT Temp Offset ALER...

Page 41: ...ach protection function The primary protection features include Cell Undervoltage Protection Cell Overvoltage Protection Cell Overvoltage Latch Protection Overcurrent in Charge Protection Overcurrent...

Page 42: ...to the BQ76942 Technical Reference Manual The secondary protection features include Safety Cell Undervoltage Permanent Fail Safety Cell Overvoltage Permanent Fail Safety Overcurrent in Charge Permanen...

Page 43: ...FETs off until the host decides to release them Alternatively the host can assert the CFETOFF or DFETOFF pins to keep the FETs off As long as these pins are asserted the FETs are blocked from being r...

Page 44: ...e DSG FET is off the device can be configured to recover when load removal is detected This feature is useful if the system has a removable pack such that the user can remove the pack from the system...

Page 45: ...3 V or 5 0 V The REG1 and REG2 LDOs and the REG0 preregulator are disabled by default in the BQ76942 device While in SHUTDOWN mode the REG1 and REG2 pins have 10 M resistances to VSS to discharge any...

Page 46: ...nterrupt output HDQ communications CFETOFF Input to control the CHG FET that is CFETOFF functionality DFETOFF Input to control the DSG FET that is DFETOFF functionality Input to control both the DSG a...

Page 47: ...he system while still providing pin control to disable the FETs The CFETOFF or BOTHOFF functionality disables both the CHG FET and the PCHG FET when asserted The DFETOFF or BOTHOFF functionality disab...

Page 48: ...is not asserted by the BQ76942 device it remains in a high impedance state and detects a voltage applied at the pin by a secondary protector The device can be configured to generate a PF if it detects...

Page 49: ...optimized features and power dissipation with the device able to transition between modes either autonomously or controlled by a host processor NORMAL mode In this mode the device performs frequent m...

Page 50: ...ent falls below a programmable current threshold the system is considered in relax mode and the BQ76942 device can autonomously transition into SLEEP mode depending on configuration 13 3 SLEEP Mode SL...

Page 51: ...s below VPORA VPORA_HYS the device transitions to SHUTDOWN mode When the device exits DEEPSLEEP mode it first completes a full measurement loop and evaluates conditions relative to enabled protections...

Page 52: ...N it generally requires approximately 200 ms 300 ms for the internal circuitry to power up load settings from OTP memory perform initial measurements evaluate those relative to enabled protections the...

Page 53: ...ting The communications interface includes programmable timeout capability this should only be used if the bus will be operating at 100 kHz or 400 kHz If this is enabled with the device set to 100 kHz...

Page 54: ...controller detects an invalid CRC the I2C controller will NACK the CRC which causes the I2C responder to go to an idle state A7 A6 A1 R7 R W R6 R0 D0 C7 C6 C0 Start Register Address Stop SCL SDA A7 A6...

Page 55: ...a falling edge of SPI_CS but it may take up to 50 s to stabilize and be available for use to the SPI interface logic this stabilization time may be longer depending on the state of the device such as...

Page 56: ...data to be written If the controller is reading then the second byte sent on SPI_MOSI is ignored except for CRC calculation If CRC is enabled then the controller must send as the third byte the 8 bit...

Page 57: ...tion 1 Using CRC SPI_MOSI SPI_CS SPI_SCLK SPI_MISO R W bit 7 bit address 2 8 bit CRC for previous two bytes R W bit 7 bit address 1 8 bit CRC for previous two bytes 8 bit write data 2 or don t care if...

Page 58: ...read data 2 Figure 14 7 SPI Transaction 3 Using CRC SPI_MISO Previous R W bit 7 bit address Previous 8 bit write or read data SPI_MOSI R W bit 7 bit address 1 8 bit write data 1 SPI_SCLK SPI_CS Figur...

Page 59: ...address 2 8 bit write data 2 or don t care if read SPI_SCLK SPI_CS Figure 14 9 SPI Transaction 2 Without CRC www ti com BQ76942 SLUSE14B DECEMBER 2020 REVISED DECEMBER 2021 Copyright 2021 Texas Instru...

Page 60: ...l For example if the device returns 0xFFFFFF on SPI_MISO then the internal clock is not powered and the transaction needs to be retried Similarly if the device returns 0xFFFFAA on a transaction this i...

Page 61: ...te for a time t B followed by a Break Recovery the host releases the HDQ interface for a time t BR 2 The next section is for host command transmission where the host transmits 8 bits by driving the HD...

Page 62: ...rrent that flows into the cell input pins on the BQ76942 device while balancing is active the measurement of cell voltages and evaluation of cell voltage protections by the device is modified during b...

Page 63: ...able the device to continue operating for a short time when a pack short circuit occurs which may cause the PACK and top of stack voltages to drop to approximately 0 V In this case the diode prevents...

Page 64: ...s are enabled charge redistribution occurs from the CP1 capacitor to the CHG and DSG capacitive FET loads This generally results in a brief drop in the voltage on CP1 which is then replenished by the...

Page 65: ...ents Example Table 16 1 BQ76942 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Minimum system operating voltage 25 V Cell minimum operating voltage 2 5 V Series cell count 10 Sense resistor 1 m Nu...

Page 66: ...to disable FET DFETOFF pin functionality Use as DFETOFF polarity normally high driven low to disable FET ALERT pin functionality Use as ALERT interrupt pin polarity driven low when active hi Z otherwi...

Page 67: ...d so a sense resistor of 1 m is suitable with a 50 ppm temperature coefficient and power rating of 1 W The REG1 is selected to provide the supply for an external host processor with output voltage sel...

Page 68: ...6942 Technical Reference Manual The device provides capability to calibrate individual cell voltage measurements stack voltage PACK pin voltage LD pin voltage current measurement and individual temper...

Page 69: ...0pF C2 100pF C16 NC 10k R15 10k R14 7P External I2C Connection 4 1 2 3 J2 PACK SDA SCL PGND E2 E1 1 2 U3 1 2 U2 PGND REG1 1 0k R13 VSS 1 0k R12 1 0k R8 1 2 J3 PEC02SAAN 5 4 1 2 3 6 7 8 9 J1 39502 1009...

Page 70: ...not connected through the series resistor to VSS on the PCB then cells cannot be connected in random sequence Each of the VC1 VC10 pins includes a diode between the pin and the adjacent lower cell inp...

Page 71: ...47 ms FULLSCAN asserted This was measured with the OTP programmed to provide the FULLSCAN bit in the Alarm signal on the ALERT pin 0 164 ms 1 97 ms FETs enabled This was measured with the OTP programm...

Page 72: ...to 200 s after which the driver remains in a high impedance state if within approximately 500 mV of the voltage of the LD pin The external resistor between the DSG gate and source then discharges the...

Page 73: ...re 16 8 A Slower Turn Off Case Using a 4 7 k Series Gate Resistor and the PACK Connector Shorted to the Top of the Stack A fast turn off case is shown in Figure 16 9 in which a 100 series gate resisto...

Page 74: ...connected to silicon They can be left floating or connected to an adjacent pin or connected to VSS 21 23 25 28 29 30 31 32 TS1 TS3 ALERT HDQ CFETOFF DFETOFF DCHG DDSG If not used these pins can be lef...

Page 75: ...ion for component placement and layout Differential Low Pass Filter and I2C communication The BQ76942 device uses an integrating delta sigma ADC for current measurements For best performance 100 resis...

Page 76: ...1 BQ76942 Example Board Layout Top Layer BQ76942 SLUSE14B DECEMBER 2020 REVISED DECEMBER 2021 www ti com 76 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated Product Folder Links...

Page 77: ...2 BQ76942 Example Board Layout Bottom Layer www ti com BQ76942 SLUSE14B DECEMBER 2020 REVISED DECEMBER 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Lin...

Page 78: ...are an engineer s go to source for fast verified answers and design help straight from the experts Search existing answers or ask your own question to get the quick design help you need Linked content...

Page 79: ...EU RoHS requirements for all 10 RoHS substances including the requirement that RoHS substance do not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures Ro...

Page 80: ...better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or...

Page 81: ...FP PFB 48 1000 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 BQ7694202PFBR TQFP PFB 48 1000 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 BQ7694203PFBR TQFP PFB 48 1000 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 BQ7694204PFBR T...

Page 82: ...4201PFBR TQFP PFB 48 1000 336 6 336 6 31 8 BQ7694202PFBR TQFP PFB 48 1000 336 6 336 6 31 8 BQ7694203PFBR TQFP PFB 48 1000 336 6 336 6 31 8 BQ7694204PFBR TQFP PFB 48 1000 336 6 336 6 31 8 BQ76942PFBR T...

Page 83: ...QUAD FLATPACK 4073176 B 10 96 Gage Plane 0 13 NOM 0 25 0 45 0 75 Seating Plane 0 05 MIN 0 17 0 27 24 25 13 12 SQ 36 37 7 20 6 80 48 1 5 50 TYP SQ 8 80 9 20 1 05 0 95 1 20 MAX 0 08 0 50 M 0 08 0 7 NOTE...

Page 84: ......

Page 85: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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