to not use too large of a value of capacitor, since this will affect the settling time when the thermistor is
biased and measured periodically. A rule of thumb is to keep the time constant of the circuit < 5% of the
measurement time. When
Settings:Configuration:Power Config[FASTADC]
= 0, the measurement time is
approximately 3 ms, and with
[FASTADC]
= 1, the measurement time is halved to approximately 1.5 ms.
When using the 18-kΩ pullup resistor with the thermistor, the time constant is generally less than (18 kΩ) × C,
so a capacitor less than 4 nF is recommended. When using the 180-kΩ pullup resistor, the capacitor should
be less than 400 pF.
• The integrated charge pump generates a voltage on the CP1 capacitor, requiring approximately 60 ms
to charge up to approximately 11 V when first enabled using the recommended 470-nF capacitor value.
When the CHG or DSG drivers are enabled, charge redistribution occurs from the CP1 capacitor to the
CHG and DSG capacitive FET loads. This generally results in a brief drop in the voltage on CP1, which is
then replenished by the charge pump. If the FET capacitive loading is large, such that at FET turn-on the
voltage on CP1 drops below an acceptable level for the application, then the value of the CP1 capacitor
can be increased. This has the drawback of requiring a longer startup time for the voltage on CP1 when
the charge pump is first powered on, and so should be evaluated to ensure it is acceptable in the system.
For example, if the CHG and DSG FETs are enabled simultaneously and their combined gate capacitance
is approximately 400 nF, then changing CP1 to a value of 2200 nF results in the 11-V charge pump level
dropping to approximately 9 V before being restored to the 11-V level by the charge pump.
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
64
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