7.30 Timing Requirements – SPI Interface (continued)
Typical values stated where T
A
= 25°C and V
BAT
= 55.0 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 55 V (unless otherwise noted). All values specified with SPI pin filtering enabled.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
R
Rise time
Up to 25pF load
30
ns
t
F
Fall time
Up to 25pF load
30
ns
t
RST
SPI bus reset
Bus interface is reset if SPI_CS
is low and SPI_SCLK is detected
unchanged for this duration
1.9
2.1
s
(1)
Specified by design
(2)
See later discussion in datasheet for more details
(3)
Specified by characterization
(4)
This assumes 15 ns setup time on the SPI controller for MISO. If additional setup time is required, the clock period should be
extended accordingly.
(5)
When SPI pin filtering is enabled, pulses on input pins of duration below 200 ns may be filtered out.
7.31 Interface Timing Diagrams
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
Figure 7-1. I
2
C Communications Interface Timing
t
TD
S
t
A
L S B O U T
t
SCK
t LEAD
t sckh
t sckl
t DIS
M S B IN
L S B IN
t HI
t SU
SPI_CS
SPI_SCLK
SPI_MISO
SPI_MOSI
t HO
t V
t R
tLAG
tF
MSB OUT
BIT
N-2
« %,7
1
BIT
N-2
« %,7
1
Figure 7-2. SPI Communications Interface Timing
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
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