Table 16-1. BQ76942 Design Requirements (continued)
DESIGN PARAMETER
EXAMPLE VALUE
OV protection threshold
4.30 V
OV protection delay
500 ms
OV protection recovery hysteresis
100 mV
UV protection threshold
2.5 V
UV protection delay
20 ms
UV protection recovery hysteresis
100 mV
SCD protection threshold
80 mV (corresponding to a nominal 80 A, based on a 1-mΩ sense resistor)
SCD protection delay
50 µs
OCD1 protection threshold
68 mV (corresponding to a nominal 68 A, based on a 1-mΩ sense resistor)
OCD1 protection delay
10 ms
OCD2 protection threshold
56 mV (corresponding to a nominal 56 A, based on a 1-mΩ sense resistor)
OCD2 protection delay
80 ms
OCD3 protection threshold
28 mV (corresponding to a nominal 28 A, based on a 1-mΩ sense resistor)
OCD3 protection delay
160 ms
OCC protection threshold
8 mV (corresponding to a nominal 8 A, based on a 1-mΩ sense resistor)
OCC protection delay
160 ms
OTD protection threshold
60°C
OTD protection delay
2 s
OTC protection threshold
45°C
OTC protection delay
2 s
UTD protection threshold
–20°C
UTD protection delay
10 s
UTC protection threshold
0°C
UTC protection delay
5 s
Host watchdog timeout protection delay
5 s
CFETOFF pin functionality
Use as CFETOFF, polarity = normally high, driven low to disable FET
DFETOFF pin functionality
Use as DFETOFF, polarity = normally high, driven low to disable FET
ALERT pin functionality
Use as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise
REG1 LDO Usage
Use for 3.3-V output
Cell balancing
Enabled when imbalance exceeds 100 mV
16.2.2 Detailed Design Procedure
• Determine the number of series cells.
– This value depends on the cell chemistry and the load requirements of the system. For example, to
support a minimum battery voltage of 25 V using Li-CO
2
type cells with a cell minimum voltage of 2.5 V,
10-series cells should be used.
– For the correct cell connections, see
Usage of VC Pins for Cells Versus Interconnect
.
• Protection FET selection and configuration
– The BQ76942 device is designed for use with high-side NFET protection (low-side protection NFETs can
be used by leveraging the DCHG / DDSG signals).
– The configuration should be selected for series Versus parallel FETs, which may lead to different FET
selection for charge Versus discharge direction.
– These FETs should be rated for the maximum:
• Voltage, which should be approximately 5 V (DC) to 10 V (peak) per series cell.
• Current, which should be calculated based on both the maximum DC current and the maximum
transient current with some margin.
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
66
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