12.11 Cell Open Wire
The BQ769142 device supports detection of a broken connection between a cell in the pack and the cell
attachment to the PCB containing BQ769142. Without this check, the voltage at the cell input pin of the
BQ769142 device may persist for some time on the board-level capacitor, leading to incorrect voltage readings.
The Cell Open Wire detection in the BQ769142 device operates by enabling a small current source from each
cell to VSS at programmable intervals. If a cell input pin is floating due to an open wire condition, this current
discharges the capacitance, causing the voltage at the pin to slowly drop. This drop in voltage eventually triggers
a protection fault on that particular cell and the cell above it. Eventually, the voltage drops low enough to trigger a
Permanent Fail on the particular cell and the cell above it.
The Cell Open Wire current is enabled at a periodic interval set by configuration register. The current source is
enabled once every interval for a duration of the ADC measurement time (which is 3 ms by default). This
provides programmability in the average current drawn from ≈0.65 nA to ≈165 nA, based on the typical current
level of 55 µA.
Note
The Cell Open Wire check can create a cell imbalance, so the settings should be selected
appropriately.
12.12 Low Frequency Oscillator
The low frequency oscillator (LFO) in the BQ769142 device operates continuously while in NORMAL and SLEEP
modes, and can be configured to remain powered or shutdown (except when needed) during DEEPSLEEP
mode. The LFO runs at ≈262.144 kHz during NORMAL mode, and reduces to ≈32.768 kHz in SLEEP or
DEEPSLEEP modes. The LFO is trimmed during manufacturing to meet the specified accuracy across
temperature.
12.13 High Frequency Oscillator
The high frequency oscillator (HFO) in the BQ769142 device operates at 16.78 MHz and is frequency locked to
the LFO. The HFO powers up as needed for internal logic functions.
13 Device Functional Modes
13.1 Overview
This device supports four functional modes to support optimized features and power dissipation, with the device
able to transition between modes either autonomously or controlled by a host processor.
• NORMAL mode: In this mode, the device performs frequent measurements of system current, cell voltages,
internal and thermistor temperature, and various other voltages, operates protections as configured, and
provides data and status updates.
• SLEEP mode: In this mode, the DSG FET is enabled, the CHG FET can optionally be disabled, and the
device performs measurements, calculations, and data updates in adjustable time intervals. Battery
protections are still enabled. Between the measurement intervals, the device is operating in a reduced power
stage to minimize total average current consumption.
• DEEPSLEEP mode: In this mode, the CHG, PCHG, DSG, and PDSG FETs are disabled, all battery
protections are disabled, and no current or voltage measurements are taken. The REG1 and REG2 LDOs
can be kept powered, in order to maintain power to external circuitry, such as a host processor.
• SHUTDOWN mode: The device is completely disabled (including the internal, REG1, and REG2 LDOs), the
CHG, PCHG, DSG, and PDSG FETs are all disabled, all battery protections are disabled, and no
measurements are taken. This is the lowest power state of the device, which may be used for shipment or
long-term storage. All register settings are lost when in SHUTDOWN mode.
The device also includes a CONFIG_UPDATE mode, which is used for parameter updates.
shows the transitions between the functional modes.
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
48
Copyright © 2021 Texas Instruments Incorporated
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