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Summary of Contents for BQ769142

Page 1: ... power tools and garden tools Non military drones Other industrial battery pack 10S 3 Description The Texas Instruments BQ769142 device is a highly integrated high accuracy battery monitor and protector for 3 series to 14 series Li ion Li polymer and LiFePO4 battery packs The device includes a high accuracy monitoring system a highly configurable protection subsystem and support for autonomous or ...

Page 2: ...10 6 Thermistor Temperature Measurement 37 10 7 Factory Trim of Voltage ADC 37 10 8 Voltage Calibration ADC Measurements 38 10 9 Voltage Calibration COV and CUV Protections 38 10 10 Current Calibration 39 10 11 Temperature Calibration 39 11 Primary and Secondary Protection Subsystems 40 11 1 Protections Overview 40 11 2 Primary Protections 40 11 3 Secondary Protections 41 11 4 High Side NFET Drive...

Page 3: ...ion A February 2021 Page Updated the short circuit in discharge voltage threshold detection accuracy characteristics in the Comparator Based Protection Subsystem section page 21 of the Specifications 7 www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links BQ769142 ...

Page 4: ...rom the bottom of the stack balance current input for the thirteenth cell from the bottom of the stack 3 VC12A I IA Return balance current for the thirteenth cell from bottom of stack This pin should be shorted to VC12B on the PCB 4 VC12B I IA Sense voltage input pin for the twelfth cell from the bottom of the stack balance current input for the twelfth cell from the bottom of the stack 5 VC11 I I...

Page 5: ... 15 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack balance current input for the first cell from the bottom of the stack and return balance current for the second cell from the bottom of the stack 16 VC0 I IA Sense voltage input pin for the negative terminal of the first cell from the bottom of the stack and return balance current for the first cell from the botto...

Page 6: ...rnal preregulator transistor 38 FUSE I O I OA Fuse sense and drive 39 PDSG O OA Predischarge PFET control 40 PCHG O OA Precharge PFET control 41 LD I O I OA Load detect pin 42 PACK I IA Pack sense input pin 43 DSG O OA NMOS Discharge FET drive output pin 44 NC This pin is not connected to silicon 45 CHG O OA NMOS Charge FET drive output pin 46 CP1 I O I OA Charge pump capacitor 47 BAT I P Primary ...

Page 7: ...DQ DCHG DDSG when used as thermistor or general purpose ADC input VSS 0 3 VREG18 0 3 V Input voltage range VIN SRP SRN VSS 0 3 VREG18 0 3 V Input voltage range VIN VC14 maximum of VSS 0 3 and VC13A 0 3 VSS 85 V Input voltage range VIN VC13A maximum of VSS 0 3 and VC13B 0 3 VSS 85 V Input voltage range VIN VC13B maximum of VSS 0 3 and VC12A 0 3 VSS 85 V Input voltage range VIN VC12A maximum of VSS ...

Page 8: ...listed under Absolute Maximum Rating may cause permanent damage to the device These are stress ratings only which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The current allowed to flow into the FUSE pin...

Page 9: ...TOFF DFETOFF DCHG DDSG except when the pin is being used for general purpose ADC input or thermistor measurement 0 5 5 V VIN Input voltage range 3 TS1 TS2 TS3 CFETOFF DFETOFF DCHG DDSG ALERT HDQ when the pin is configured for general purpose ADC input or thermistor measurement 0 VREG18 V VIN Input voltage range 3 SRP SRN SRP SRN while measuring current 0 2 0 2 V VIN Input voltage range 3 SRP SRN w...

Page 10: ... for best performance 7 4 Thermal Information bq769142 THERMAL METRIC 1 BQ769142 UNIT PFB TQFP 48 PINS RθJA Junction to ambient thermal resistance 66 0 C W RθJC top Junction to case top thermal resistance 19 6 C W RθJB Junction to board thermal resistance 29 3 C W ΨJT Junction to top characterization parameter 0 8 C W ΨJB Junction to board characterization parameter 29 1 C W 1 For more information...

Page 11: ... SCL SDA HDQ CFETOFF DFETOFF RST_SHUT 0 33 x VREG18 V VOH Output voltage high TS2 TS2 during SHUTDOWN mode VBAT 6 V 4 5 6 V VOH Output voltage high TS2 low voltage TS2 during SHUTDOWN mode 4 7 V VBAT 6 V 3 6 V VOH Output voltage high 5 V case ALERT SDA configured as SPI_MISO SCL configured as SPI_SCLK CFETOFF configured as GPO DFETOFF configured as GPO DCHG DDSG pins driving from REG1 VREG1 set to...

Page 12: ...harge pump is not in operation Whenever the charge pump is in operation in 5 5 V or 11 V mode the maximum voltage on VBAT should be reduced to ensure the voltage on CP1 CHG and DSG does not exceed their maximum specified voltage 7 9 FUSE Pin Functionality Typical values stated where TA 25 C and VBAT 59 2 V min max values stated where TA 40 C to 85 C and VBAT 4 7 V to 80 V unless otherwise noted 1 ...

Page 13: ...IN at 25 C IREGIN 50 mA VBAT 8 V 0 05 IMax Maximum current driven out from BREG 4 Under short circuit conditions VREGIN 0 V 2 5 3 33 mA CEXT External capacitor REGIN to VSS 3 4 15 22 27 nF CBREG External capacitor BREG to VSS 4 150 pF 1 Operation with VBAT up to 80 V is supported when the charge pump is not in operation Whenever the charge pump is in operation in 5 5 V or 11 V mode the maximum vol...

Page 14: ...VREG2 set to nominal 3 3 V setting 0 25 ΔVO LINE Line regulation ΔVREG2 vs VREG2 at 25 C VREGIN 5 5 V IREG2 20 mA as VREGIN varies from 5 V to 6 V VREG2 set to nominal 3 3 V setting 1 1 ISC Regulator short circuit current limit VREG2 0 V 47 80 mA CEXT External capacitor REG2 to VSS 2 1 µF 1 Operation with VBAT up to 80 V is supported when the charge pump is not in operation Whenever the charge pum...

Page 15: ...ied by characterization 4 Specified by design 7 16 Coulomb Counter Digital Filter CC1 Typical values stated where TA 25 C and VBAT 59 2 V min max values stated where TA 40 C to 85 C and VBAT 4 7 V to 80 V unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t CC1_CONV_FAST Conversion time Single conversion when operating from LFO in 262 144kHz mode 250 ms t CC1_CONV_SLOW Conversion ...

Page 16: ... 2 12 ms 1 Operation with VBAT up to 80 V is supported when the charge pump is not in operation Whenever the charge pump is in operation in 5 5 V or 11 V mode the maximum voltage on VBAT should be reduced to ensure the voltage on CP1 CHG and DSG does not exceed their maximum specified voltage 2 Specified by design 7 19 Analog to Digital Converter Typical values stated where TA 25 C and VBAT 59 2 V...

Page 17: ...DC_RES Code stability 2 4 Single conversion in NORMAL mode Settings Configuration Power Config FASTADC 0 13 5 15 bits B ADC_RES_FAST Code stability in fast mode 2 Single conversion in NORMAL mode Settings Configuration Power Config FASTADC 1 14 bits t ADC_CONV Conversion time Single conversion in NORMAL mode Settings Configuration Power Config FASTADC 0 2 93 ms t ADC_CONV_FAST Conversion time in f...

Page 18: ...re TA 40 C to 85 C and VBAT 4 7 V to 80 V unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V TEMP Internal temperature sensor voltage drift ΔVBE measurement 0 410 mV C 1 Operation with VBAT up to 80 V is supported when the charge pump is not in operation Whenever the charge pump is in operation in 5 5 V or 11 V mode the maximum voltage on VBAT should be reduced to ensure the vol...

Page 19: ...BAT up to 80 V is supported when the charge pump is not in operation Whenever the charge pump is in operation in 5 5 V or 11 V mode the maximum voltage on VBAT should be reduced to ensure the voltage on CP1 CHG and DSG does not exceed their maximum specified voltage 2 Specified by design 3 Specified by a combination of design and production test 7 25 High side NFET Drivers Typical values stated wh...

Page 20: ...nsure the voltage on CP1 CHG and DSG does not exceed their maximum specified voltage 2 When the DSG driver is enabled the CHG driver is disabled and a voltage is applied at the LD pin such that VLD VDSG the voltage at DSG will rise to VLD 0 7 V 3 Specified by design 4 Specified by characterization 5 RGATE can be optimized during design and system evaluation for best performance A larger value may ...

Page 21: ...between 1 518 V and 3 542 V 2 25 25 mV V UVP_DLY Undervoltage detection delay 3 Nominal setting 3 3 ms steps 10 ms to 6753 ms in 3 3 ms steps ms V SCD Short circuit in discharge voltage threshold range Nominal settings threshold based on VSRP VSRN 10 20 40 60 80 100 125 150 175 200 250 300 350 400 450 500 mV V SCD_ACC Short circuit in discharge voltage threshold detection accuracy 4 TA 40 C to 85 ...

Page 22: ... and VBAT 4 7 V to 80 V unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Clock operating frequency 2 SCL duty cycle 50 100 kHz tHD STA START condition hold time 2 4 0 µs tLOW Low period of the SCL clock 2 4 7 µs tHIGH High period of the SCL clock 2 4 0 µs tSU STA Setup repeated START 2 4 7 µs tHD DAT Data hold time SDA input 2 0 ns tSU DAT Data setup time SDA input 2 250 ns...

Page 23: ...nd VBAT 4 7 V to 80 V unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tB Break Time 2 190 µs tBR Break Recovery Time 2 40 µs tHW1 Host Write 1 Time 2 Host drives HDQ 0 5 50 µs tHW0 Host Write 0 Time 2 Host drives HDQ 86 145 µs tCYCH Cycle Time Host to device 2 Device drives HDQ 190 µs tCYCD Cycle Time device to Host 2 Device drives HDQ 190 205 250 µs tDW1 Device Write 1 Time 2 ...

Page 24: ... Operation with VBAT up to 80 V is supported when the charge pump is not in operation Whenever the charge pump is in operation in 5 5 V or 11 V mode the maximum voltage on VBAT should be reduced to ensure the voltage on CP1 CHG and DSG does not exceed their maximum specified voltage 2 Specified by design 3 See later discussion in datasheet for more details 4 Specified by characterization 5 This as...

Page 25: ... HDQ Host response format f HDQ Host to Device e Device to HDQ Host Response t RST f HDQ Reset 7 bit address 1 bit R W 7 bit address t RSPS Break d Device Transmitted Bit c HDQ Host Transmitted Bit T HW1 T HW0 T CYCH T DW1 T DW0 T CYCD 1 2 V t B t BR b HDQ Line Rise Time a Break and Break Recovery t RISE Figure 7 3 HDQ Communications Interface Timing www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REV...

Page 26: ... with Cell Voltage 2 5 V Figure 7 7 Cell Voltage Measurement Error vs Temperature with Cell Voltage 3 5 V Figure 7 8 Cell Voltage Measurement Error vs Temperature with Cell Voltage 4 5 V Figure 7 9 Cell Voltage Measurement Error vs Temperature with Cell Voltage 5 5 V BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 26 Submit Document Feedback Copyright 2021 Texas Instruments Incor...

Page 27: ...erature VREF1 and VREF2 Figure 7 12 Internal Temperature Sensor Delta VBE Voltage vs Temperature LFO measured in full speed mode 262 kHz Figure 7 13 Low Frequency Oscillator LFO Accuracy vs Temperature www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links BQ769142 ...

Page 28: ...e This test uses a resistor divider across the VCx pins to allow for one common voltage to be scaled across the cell inputs The top of the string is swept and captured as the Cell Voltage Figure 7 18 Cell Balancing Resistance vs Cell Common mode Voltage at 25 C Figure 7 19 REG1 Voltage vs Load at 25 C BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 28 Submit Document Feedback Cop...

Page 29: ... calculated as percentage of nominal gain across 200 mV input range Figure 7 23 Coulomb Counter Gain Error vs Temperature Figure 7 24 LD Wake Voltage vs Temperature Figure 7 25 REG18 Voltage vs Temperature with No Load www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links BQ769142 ...

Page 30: ...s Temperature Figure 7 29 BAT Current in SHUTDOWN Mode vs Temperature Figure 7 30 BAT Current in SLEEP2 SRC Follower Mode vs Temperature Figure 7 31 BAT Current in DEEPSLEEP2 No LFO Mode vs Temperature BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 30 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated Product Folder Links BQ769142 ...

Page 31: ...customers to setup device operation on their own production line Multiple communications interfaces are supported including 400 kHz I2C SPI and HDQ one wire standards Multiple digital control and status data are available through several multifunction pins on the device including an interrupt to the host processor and independent controls for host override of each high side protection NFET Three d...

Page 32: ...ADCIN GPO DCHG TS ADCIN GPO HDQ SPI_MOSI TS ADCIN GPO FUSE FUSE Driver CHG DSG Drivers REG18 CP1 PCHG Driver PDSG Driver CHG PCHG PDSG DSG Charger Detect Load Detect BAT BAT Charge Pump To Digital To Digital CHG DSG drivers PACK BAT 8 4 Diagnostics The BQ769142 device includes a suite of diagnostic tests the system can use to increase operational robustness These tests include comparisons between ...

Page 33: ...gs can be changed Data memory settings cannot be changed directly UNSEALED mode includes SEALED functionality and also adds the ability to execute additional subcommands and read and write data memory FULLACCESS mode allows capability to read and modify all device settings including writing OTP memory Selected settings in the device can be modified while the device is in operation through supporte...

Page 34: ...abled measurement slots The speed of a measurement loop can be controlled by settings Each voltage measurement slot takes 3 ms or 1 5 ms depending on setting so a typical measurement loop with 21 slots per loop takes 63 ms or 31 5 ms depending on setting If measurement data is not required as quickly the timing for the measurement loop can be programmed to slower speeds which injects idle slots in...

Page 35: ... to measure interconnect or are not used at all Voltage measurements for all inputs are reported in 16 bit format in units of mV as well as 32 bit format in units of raw ADC counts irrespective of whether they are used for cells or not 10 2 General Purpose ADCIN Functionality Several multifunction pins on the BQ769142 device can be used for general purpose ADC input ADCIN measurement if not being ...

Page 36: ...4 bit current measurement that is used for current reporting with one output every 3 ms when the device is operating in NORMAL mode which can be reduced to one output every 1 5 ms based on setting with reduced measurement resolution It is reported in 16 bit format and the 24 bit CC2 data is also available as raw coulomb counter ADC counts provided in a 32 bit format with the data contained in the ...

Page 37: ...0 Ÿ 500 Ÿ 500 Ÿ 500 Ÿ 500 Ÿ 500 Ÿ 500 Ÿ 500 Ÿ 500 Ÿ VREF1 Figure 10 3 External Thermistor Biasing To provide a high precision temperature result the device uses the same 1 8 V LDO voltage for the ADC reference as is used for biasing the thermistor pullup resistor thereby implementing a ratiometric measurement that removes the error contribution from the LDO voltage level The device processes the d...

Page 38: ...ot been overwritten While in CONFIG_UPDATE mode the Cell Gain values will read back either with all zeros if they have not been overwritten or whatever values have been written to these registers Upon exiting CONFIG_UPDATE mode readback of the Cell Gain parameters will provide the values presently used in operation Further details on calibration procedures can be found in the BQ769142 Technical Re...

Page 39: ...plied by Calibration Current CC Gain and scaled to provide the final result in units of userA The BQ769142 device uses the Calibration Current CC Gain and Calibration Current Capacity Gain configuration values to convert from the ADC value to current The CC Gain reflects the value of the sense resistor used in the system while the Capacity Gain is simply the CC Gain multiplied by 298261 6178 Both ...

Page 40: ...lement a precharge and predischarge functionality The secondary protection suite within the BQ769142 device can react to more serious faults and take action to permanently disable the pack by initiating a Permanent Fail PF The secondary safety provides protection against safety cell undervoltage and overvoltage safety overcurrent in charge and discharge safety overtemperature for cells and FETs ex...

Page 41: ...ose options are enabled When a Permanent Fail occurs the device may be configured to either turn the REG1 and REG2 LDOs off or to leave them in their present state Once disabled they may still be reenabled through command The Permanent Fail checks incorporate a programmable delay to avoid triggering a PF fault on an intermittent condition or measurement When the threshold is first detected as bein...

Page 42: ...figuration setting In general the 5 5 V setting results in lower power dissipation when a FET is being driven while the higher 11 V overdrive reduces the on resistance of the FET If a FET exhibits significant gate leakage current when driven at the higher overdrive level this can result in a higher device current for the charge pump to support this In this case using the lower overdrive level can ...

Page 43: ...RGE and PREDISCHARGE Modes The BQ769142 device includes precharge functionality which can be used to reduce the charging current for an undervoltage battery by charging using a high side PCHG PFET driven from the PCHG pin with series resistor until the battery reaches a programmable voltage level When the minimum cell voltage is less than a programmable threshold the PCHG FET will be used for char...

Page 44: ...LDOs can provide an output current of up to 45 mA each 12 3 1 Preregulator Control The REG1 and REG2 LDOs take their input from the REGIN pin which should be approximately 5 5 V This REGIN pin voltage can be supplied externally such as by a separate DC DC converter or using the integrated voltage preregulator referring to as REG0 which drives the base of an external NPN BJT using the BREG pin to p...

Page 45: ...tail below 12 5 Multifunction Pin Controls The BQ769142 device provides flexibility regarding the multifunction pins on the device which includes the TS1 TS2 TS3 CFETOFF DFETOFF ALERT HDQ DCHG and DDSG pins Several of the pins can be used as active high outputs with configurable output level The digital output driver for these pins can be configured to drive an output powered from the REG1 LDO or ...

Page 46: ...FETs and the DFETOFF pin can optionally be used to disable the DSG and PDSG FETs The device also includes the option to configure the DFETOFF pin as BOTHOFF functionality such that if that pin is asserted the CHG PCHG DSG and PDSG FETs will be disabled This allows the CFETOFF pin to be used for an additional thermistor in the system while still providing pin control to disable the FETs The CFETOFF...

Page 47: ...OFF and DFETOFF pins 12 10 Fuse Drive The FUSE pin on the BQ769142 device can be used to blow a chemical fuse in the presence of a Permanent Fail PF as well as to determine if an external secondary protector in the system has detected a fault and is attempting to blow the fuse itself The pin can drive the gate of an NFET which can be combined with the drive from an external secondary protector as ...

Page 48: ...e high frequency oscillator HFO in the BQ769142 device operates at 16 78 MHz and is frequency locked to the LFO The HFO powers up as needed for internal logic functions 13 Device Functional Modes 13 1 Overview This device supports four functional modes to support optimized features and power dissipation with the device able to transition between modes either autonomously or controlled by a host pr...

Page 49: ...harging is underway When the CC1 Current measurement falls below a programmable current threshold the system is considered in RELAX mode and the BQ769142 device can autonomously transition into SLEEP mode depending on the configuration 13 3 SLEEP Mode SLEEP mode is a reduced functionality state that can be optionally used to reduce power dissipation when there is little or no system load current o...

Page 50: ...d or if a charger is attached which is detected by the voltage on the LD pin rising from below VWAKEONLD to exceed it In addition if the BAT pin voltage falls below VPORA VPORA_HYS the device transitions to SHUTDOWN mode When the device exits DEEPSLEEP mode it first completes a full measurement loop and evaluates conditions relative to enabled protections to ensure that conditions are acceptable t...

Page 51: ...initial measurements evaluate those relative to enabled protections then to enable FETs if conditions allow This can be much longer depending on settings The BQ769142 device integrates a hardware overtemperature detection circuit which determines when the die temperature passes an excessive temperature of approximately 120 C If this detector triggers the device automatically begins the sequence to...

Page 52: ...en the device will reset the communications interface logic if a clock is detected low longer than a tTIMEOUT of 25 ms to 35 ms or if the cumulative clock low slave extend time exceeds 25 ms or if the cumulative clock low master extend time exceeds 10 ms If the timeouts are enabled with the device set to 400 kHz mode then the device will reset the communications interface logic if a clock is detec...

Page 53: ...n the master detects an invalid CRC the I2C master will NACK the CRC which causes the I2C slave to go to an idle state A7 A6 A1 R7 R W R6 R0 D0 C7 C6 C0 Start Slave Address Register Address Stop SCL SDA A7 A6 A1 R W ACK ACK ACK D7 D6 ACK NACK Slave Address Slave Drives CRC optional Master Drives NACK Slave Drives Data Stop Start Figure 14 3 I2C Read Without Repeated Start 14 3 SPI Communications T...

Page 54: ...e device will automatically wake the internal oscillator at a falling edge of SPI_CS but it may take up to 50 µs to stabilize and be available for use to the SPI interface logic The address 0x7F used in the device is defined in such a manner that there should be no valid transaction to write 0xFF into this address Thus the two byte pattern 0xFFFF should never occur as a valid sequence in the first...

Page 55: ...ll be the data to be written If the master is reading then the second byte sent on SPI_MOSI is ignored except for CRC calculation If CRC is enabled then the master must send as the third byte the 8 bit CRC code which is calculated over the first two bytes If the CRC is correct then the values clocked in will be put into the incoming buffer If the CRC is not correct then the outgoing buffer will be...

Page 56: ...ion 1 Using CRC SPI_MOSI SPI_CS SPI_SCLK SPI_MISO R W bit 7 bit address 2 8 bit CRC for previous two bytes R W bit 7 bit address 1 8 bit CRC for previous two bytes 8 bit write data 2 or don t care if read 8 bit write data 1 Figure 14 6 SPI Transaction 2 Using CRC BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 56 Submit Document Feedback Copyright 2021 Texas Instruments Incorpora...

Page 57: ...read data 2 Figure 14 7 SPI Transaction 3 Using CRC SPI_MISO Previous R W bit 7 bit address Previous 8 bit write or read data SPI_MOSI R W bit 7 bit address 1 8 bit write data 1 SPI_SCLK SPI_CS Figure 14 8 SPI Transaction 1 Without CRC www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links BQ7...

Page 58: ...ddress 2 8 bit write data 2 or don t care if read SPI_SCLK SPI_CS Figure 14 9 SPI Transaction 2 Without CRC BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 58 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated Product Folder Links BQ769142 ...

Page 59: ...f the device returns 0xFFFFFF on SPI_MISO then the internal clock was not powered and the transaction will need to be retried Similarly if the device returns 0xFFFFAA on a transaction this indicates the previous transaction encountered a CRC error and so the previous transaction must be retried And as described above if the device returns 0xFFFF00 then the previous transaction had not completed wh...

Page 60: ...hich can optionally balance cells autonomously without requiring any interaction with a host processor Or if preferred balancing can be entirely controlled manually from a host processor For autonomous balancing the device will only balance non adjacent cells in use it does not consider inputs used to measure interconnect as cells in use To avoid excessive power dissipation within the BQ769142 dev...

Page 61: ...igger thresholds for protection enable or disable of certain features for operation configuration of cells and more are known This results in a golden image of settings which can then be programmed into the device registers or OTP memory 16 2 Typical Applications Figure 16 1 shows a simplified application schematic for a 14 series battery pack using the BQ769142 together with an external secondary...

Page 62: ...keep the time constant of the circuit 5 of the measurement time When Settings Configuration Power Config FASTADC 0 the measurement time is approximately 3 ms and with FASTADC 1 the measurement time is halved to approximately 1 5 ms When using the 18 kΩ pullup resistor with the thermistor the time constant will generally be less than 18 kΩ C so a capacitor less than 4 nF is recommended When using t...

Page 63: ...769142 for a 14 series battery pack The BQ76952 EVM also provides a good reference design for BQ769142 noting that the VC12 VC16 connections in the BQ76952 EVM need to be modified as shown in Figure 16 1 www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links BQ769142 ...

Page 64: ...220nF C21 220nF C22 VC0 16 VC1 15 VC2 14 VC3 13 VC4 12 VC5 11 VC6 10 VC7 9 VC8 8 VC9 7 VC10 6 VC11 5 VC12A 3 VC12B 4 VC13A 1 VC13B 2 VC14 48 TS1 21 TS2 22 TS3 23 REG1 35 REG2 34 REG18 24 ALERT 25 BAT 47 BREG 37 CFETOFF 29 CHG 45 CP1 46 DCHG 31 DDSG 32 DFETOFF 30 DSG 43 FUSE 38 HDQ 28 LD 41 PACK 42 PCHG 40 PDSG 39 REGIN 36 RST_SHUT 33 SCL 26 SDA 27 SR N 20 SRP 18 N C 19 NC 44 VSS 17 BQ769142PFBR U1...

Page 65: ...esistor OCD1 protection delay 10 ms OCD2 protection threshold 56 mV corresponding to a nominal 56 A based on a 1 mΩ sense resistor OCD2 protection delay 80 ms OCD3 protection threshold 28 mV corresponding to a nominal 28 A based on a 1 mΩ sense resistor OCD3 protection delay 160 ms OCC protection threshold 8 mV corresponding to a nominal 8 A based on a 1 mΩ sense resistor OCC protection delay 160 ...

Page 66: ...ing the normal maximum charge or discharge current the sense resistor 200 mV 20 0 A 10 mΩ maximum However considering a short circuit discharge current of 80 A the recommended maximum SRP SRN voltage of 0 75 V and the maximum SCD threshold of 500 mV the sense resistor should be below 500 mV 80 A 6 25 mΩ maximum Further tolerance analyses value tolerance temperature variation and so on and the PCB ...

Page 67: ...e however some restrictions to how the cells are connected during manufacturing To avoid misunderstanding note that the cells in a stack cannot be randomly connected to any VC pin on the device such as the lowest cell cell 1 connected to VC13A while the top cell cell 14 is connected to VC4 and so on It is important that the cells in the stack be connected in ascending pin order with the lowest cel...

Page 68: ...as available earlier Table 16 2 Startup Sequence and Timing Step Comment FASTADC Setting Time relative to wakeup event Wakeup event Either the TS2 pin is pulled low or the LD pin is pulled up triggering the device to exit SHUTDOWN mode 0 1 0 REG1 powered This was measured with the OTP programmed to autonomously power the REG1 LDO 0 1 20 ms INITSTART asserted This was measured with the OTP programm...

Page 69: ...D pin voltage This repeats in a series of pulses which over time discharge the DSG gate to the voltage of the LD pin This pulsing continues for approximately 100 to 200 μs after which the driver remains in a high impedance state if within approximately 500 mV of the voltage of the LD pin The external resistor between the DSG gate and source then discharges the remaining FET VGS voltage so the FET ...

Page 70: ...shorted to the top of stack Figure 16 7 Zoomed In View of the Pulsing on the DSG Pin During FET Turn Off A slower turn off case is shown in Figure 16 8 using a 4 7 kΩ series gate resistor and the PACK connector shorted to the top of stack BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 70 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated Product Folder Links ...

Page 71: ...n the DSG pin and the FET gate Figure 16 9 A Fast Turn Off Case with a 100 Ω Series Gate Resistor 16 6 Unused Pins Some device pins may not be needed in a particular application The manner in which each should be terminated in this case is described below www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 71 Prod...

Page 72: ...lso not used both pins should be connected to pin 17 VSS If this pin is not used but pin 36 is used such as driven from an external source then this pin should be connected to pin 36 REGIN 38 FUSE If not used this pin can be left floating or connected to pin 17 VSS 39 PDSG If not used this pin should be left floating 40 PCHG If not used this pin should be left floating 41 LD If the DSG driver will...

Page 73: ...al decoupling capacitor which should be placed as close to the REG18 pin as possible with minimized trace inductance and connected to a ground plane electrically connected to VSS The I2C clock and data pins have integrated ESD protection circuits however adding a Zener diode and series resistor on each pin provides more robust ESD performance 18 2 Layout Example An example circuit layout using the...

Page 74: ...1 BQ76952 Two Layer Board Layout Top Layer BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 www ti com 74 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated Product Folder Links BQ769142 ...

Page 75: ...BQ76952 Two Layer Board Layout Bottom Layer www ti com BQ769142 SLUSE91A SEPTEMBER 2020 REVISED FEBRUARY 2021 Copyright 2021 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links BQ769142 ...

Page 76: ...property of their respective owners 19 5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrate...

Page 77: ...retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature 4 There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 5 Multiple Device Markings will be inside parentheses Only one Dev...

Page 78: ... QUAD FLATPACK 4073176 B 10 96 Gage Plane 0 13 NOM 0 25 0 45 0 75 Seating Plane 0 05 MIN 0 17 0 27 24 25 13 12 SQ 36 37 7 20 6 80 48 1 5 50 TYP SQ 8 80 9 20 1 05 0 95 1 20 MAX 0 08 0 50 M 0 08 0 7 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

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Page 80: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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