If an excessive number of SPI transactions occur over a long period of time, the device may experience a
watchdog fault. It is recommended to limit the frequency of SPI transactions by providing 50 μs or more from the
end of one transaction to the start of a new transaction.
The device includes ability to detect a frozen or disconnected SPI bus condition, and it will then reset the bus
logic. This condition is recognized when the SPI_CS is low and the SPI_SCLK is static and not changing for a
two second timeout.
Depending on the version of the device being used, the SPI_MISO pin may be configured by default to use the
REG18 LDO for its output drive, which will result in a 1.8-V signal level. This may cause communications errors if
the host processor operates with a higher voltage, such as 3.3 V or 5 V. The SPI_MISO pin can be programmed
to instead use the REG1 LDO for its output drive by setting the
Settings:Configuration:SPI
Configuration[MISO_REG1]
data memory configuration bit. This bit should only be set if the REG1 LDO is
powered. After this bit has been modified, it is necessary to send the
SWAP_TO_SPI()
or
SWAP_COMM_MODE()
subcommands for the device to use the new value.
The device includes optional pin filtering on the SPI input pins, which implements a filter with approximately 200-
ns delay on each input pin. This filtering is enabled by default but can be disabled by clearing the
Settings:Configuration:SPI Configuration[FILT]
data memory configuration bit.
14.3.1 SPI Protocol
The first byte of a SPI transaction consists of an R/W bit (R=0, W=1), followed by a 7-bit address, MSB-first. If
the master (host) is writing, then the second byte will be the data to be written. If the master is reading, then the
second byte sent on SPI_MOSI is ignored (except for CRC calculation).
If CRC is enabled, then the master must send as the third byte the 8-bit CRC code, which is calculated over the
first two bytes. If the CRC is correct, then the values clocked in will be put into the incoming buffer. If the CRC is
not correct, then the outgoing buffer will be set to 0xFFFF, and the outgoing CRC will be set to 0xAA (these are
clocked out on the next transaction).
During this transaction, the logic will clock out the contents of the outgoing buffer. If the outgoing buffer has not
been updated since the last transaction, then the logic will clock out 0xFFFF, and if the CRC is clocked, it will
clock out 0x00 for the CRC (if enabled). Thus the 0xFFFF00 will indicate to the master that the outgoing buffer
was not updated by the internal logic before the transaction occurred. This can occur when the device did not
have sufficient time to update the buffer between consecutive transactions.
When the internal logic takes the write-data from the interface logic and processes it, it also causes the R/W bit,
address, and data to be copied into the outgoing buffer. On the next transaction, this data is clocked back to the
master.
When the master is initiating a read, the internal logic will put the R/W bit and address into the outgoing buffer,
along with the data requested. The interface will compute the CRC on the two bytes in the outgoing buffer and
clock that back to the master if CRC is enabled (with the exceptions associated with 0xFFFF as noted above). A
diagram of three transaction sequences with and without CRC are shown below, assuming CPOL=0.
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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