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Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
B
(CC2_RES)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[FASTADC]
= 0
14
15
bits
B
(CC2_RES_FAST)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[FASTADC]
= 1
13.5
bits
(1)
Operation with V
BAT
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
5.5 V or 11 V mode), the maximum voltage on V
BAT
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
their maximum specified voltage.
(2)
Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.
(3)
Specified by characterization
7.18 Current Wake Detector
Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
WAKE_THR
Wakeup voltage threshold error
T
A
= 25°C, V
WAKE
= V
SRP
– V
SRN
, setting
between ±0.5 mV and ±5 mV. Measured
using averaged data to remove effects of
noise.
-200
200
µV
V
WAKE_THR
Wakeup voltage threshold error
T
A
= 25°C, V
WAKE
= V
SRP
– V
SRN
, setting
beyond ±5 mV. Measured using
averaged data to remove effects of noise.
-5
5
% of
setting
t
WAKE
12
ms
(1)
Operation with V
BAT
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
5.5 V or 11 V mode), the maximum voltage on V
BAT
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
their maximum specified voltage.
(2)
Specified by design
7.19 Analog-to-Digital Converter
Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
(ADC_IN_CELLS)
Input voltage range
(differential cell input
mode)
Internal reference (Vref = V
REF1
)
–0.2
5.5
V
V
(ADC_IN)
Input voltage range
(ADCIN measurement
mode)
Internal reference (Vref = V
REF1
), applicable
to ADCIN measurements using the TS1, TS2,
TS3, ALERT, CFETOFF, DFETOFF, HDQ,
DCHG, and DDSG pins
–0.2
V
REG18
V
V
(ADC_IN_TS)
Input voltage range
(external thermistor
measurement mode)
Regulator reference (Vref = V
REG18
),
applicable to external thermistor
measurements using the TS1, TS2, TS3,
ALERT, CFETOFF, DFETOFF, HDQ, DCHG,
and DDSG pins
–0.2
V
REG18
V
V
(ADC_IN_DIV)
Input voltage range
(divider measurement
mode)
Internal reference (Vref = V
REF1
), applicable
to divider measurements using the VC14,
PACK, and LD pins relative to VSS.
–0.2
80
V
B
(ADC_INL)
Integral nonlinearity
(when using V
REF1
and differential cell
voltage measurement
mode at VC14 -
VC13A)
16-bit, best fit over -0.1 V to 5.5 V
–6.6
6.6
LSB
16-bit, best fit over -0.2 V to 0.2 V
–4
4
LSB
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
16
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