Texas Instruments BQ769142, Manual

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7.30 Timing Requirements - SPI Interface
Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted). All values specified with SPI pin filtering enabled.
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
SCK
SPI clock period
(2)
500
(5)
ns
t
LEAD
Enable lead-time
(2)
625 ns
t
LAG
Enable lag time
(2)
50 ns
t
TD
Sequential transfer delay
(3)
50 µs
t
SU
Data setup time
(2) (6)
50 ns
t
HI
Data hold time (inputs)
(2) (6)
50 ns
t
HO
Data hold time (outputs)
(2)
0 ns
t
A
Slave access time
(2)
500 ns
t
DIS
Slave DOUT disable time
(2)
450 ns
t
V
Data valid
(2)
235
(5)
ns
t
R
Rise time
(2)
Up to 25pF load 30 ns
t
F
Fall time
(2)
Up to 25pF load 30 ns
t
RST
SPI bus reset
(2)
Bus interface is reset if SPI_CS is
low and SPI_SCLK is detected
unchanged for this duration
1.9 2.1 s
(1) Operation with V
BAT
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
5.5 V or 11 V mode), the maximum voltage on V
BAT
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
their maximum specified voltage.
(2) Specified by design
(3) See later discussion in datasheet for more details
(4) Specified by characterization
(5) This assumes 15 ns setup time on the SPI master for MISO. If additional setup time is required, the clock period should be extended
accordingly.
(6) When SPI pin filtering is enabled, pulses on input pins of duration below 200 ns may be filtered out.
7.31 Interface Timing Diagrams
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
Figure 7-1. I
2
C Communications Interface Timing
BQ769142
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
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