t
TD
S
t
A
L S B O U T
t
SCK
t LEAD
t sckh
t sckl
t DIS
M S B IN
L S B IN
t HI
t SU
SPI_CS
SPI_SCLK
SPI_MISO
SPI_MOSI
t HO
t V
t R
tLAG
tF
MSB OUT
BIT
N-2
« %,7
1
BIT
N-2
« %,7
1
Figure 7-2. SPI Communications Interface Timing
a. HDQ Breaking
b. Rise time of HDQ line
c. HDQ Host to Device communication
d. Device to HDQ Host communication
e. Device to HDQ Host response format
f. HDQ Host to Device
(e) Device to HDQ Host Response
t
(RST)
(f) HDQ Reset
7-bit address
1-bit
R/W
7-bit address
t
(RSPS)
Break
(d) Device Transmitted Bit
(c) HDQ Host Transmitted Bit
T
(HW1)
T
(HW0)
T
(CYCH)
T
(DW1)
T
(DW0)
T
(CYCD)
1.2 V
t
(B)
t
(BR)
(b) HDQ Line Rise Time
(a) Break and Break Recovery
t
(RISE)
Figure 7-3. HDQ Communications Interface Timing
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated
25
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