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Figure 16-6. Moderate Speed DSG FET Turn-Off, Using a 1-kΩ Series Gate Resistor, and a Light Load on
PACK+.
A zoomed-in version of the pulsing generated by the DSG pin is shown in
, this time with PACK+
shorted to the top of stack.
Figure 16-7. Zoomed-In View of the Pulsing on the DSG Pin During FET Turn-Off
A slower turn-off case is shown in
, using a 4.7-kΩ series gate resistor, and the PACK+ connector
shorted to the top of stack.
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
70
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