Texas Instruments BQ25123, Manual

Page: 5 / 72

Table 7-1. Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
LS/LDO C5 O
Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to
assure stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor.
LSCTRL E3 I
Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to
disable the LS/LDO output.
MR E1 I
Manual Reset Input. MR is a push-button input that must be held low for greater than t
RESET
to assert the reset output. If MR is pressed for a shorter period, there are two programmable
timer events, t
WAKE1
and t
WAKE2
, that trigger an interrupt to the host. The MR input can also
be used to bring the device out of Ship mode.
PG D4 O
Open-drain Power Good status indication output. PG pulls to GND when V
IN
is above
V
(BAT)
+ V
SLP
and less that V
OVP
. PG is high-impedance when the input power is not within
specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,
or use with an LED for visual indication. PG can also be configured as a push-button voltage
shifted output (MRS) in the registers, where the output of the PG pin reflects the status of
the MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.
PGND A5 -
Power ground connection. Connect to the ground plane of the circuit. Connect the output
filter cap from the buck converter to this ground as shown in the layout example.
PMID A3, B3 I/O
High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias
derating from PMID to GND as close to the PMID and GND pins as possible. When entering
Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.
RESET D3 O
Reset Output. RESET is an open drain active low output that goes low when MR is held
low for longer than t
RESET
, which is configurable by the MRRESET registers. RESET is
deasserted after the t
RESET_D,
typically 400ms.
SCL E5 I I
2
C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA E4 I/O I
2
C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
SW A4 O Inductor Connection. Connect to the switched side of the external inductor.
SYS B5 I
System Voltage Sense Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.
TS C3 I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to
GND. The NTC is connected from TS to GND. The TS function provides four thresholds for
JEITA compatibility. TS faults are reported by the I
2
C interface during charge mode.
VINLS B4, C4 I
Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from
this pin to GND.
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BQ25123
SLUSCZ6A – JANUARY 2018 – REVISED MAY 2021
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