The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see
). This releases the bus and stops the communication
link with the addressed slave. All I
2
C compatible devices must recognize the STOP condition. Upon the receipt
of a STOP condition, all devices know that the bus is released, and wait for a START condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I
2
C logic from remaining in an incorrect state. Attempting to read data from register addresses
not listed in this section results in 0xFFh being read out.
SDA
SCL
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
MSB
Address
R/W
ACK
S
or
Sr
Sr
or
P
P
Sr
ACK
Figure 9-10. Bus Protocol
SLUSCZ6A – JANUARY 2018 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
33
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