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11 Layout

11.1 Layout Guidelines

• Keep the core components of the system close to each other and the device.
• Keep the PMID, IN, and SYS caps as close to their respective pins as possible. Place the bypass caps for

PMID, SYS, and LSLDO close to the pins.

• Place the GNDs of the PMID and IN caps close to each other.
• Do not route so the power planes are interrupted.

11.2 Layout Example

Figure 11-1. BQ25123 Layout

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BQ25123

SLUSCZ6A – JANUARY 2018 – REVISED MAY 2021

Copyright © 2021 Texas Instruments Incorporated

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BQ25123

Summary of Contents for BQ25123

Page 1: ...output voltage adjustment 2 Applications Smart watches and other wearable devices Fitness accessories Health monitoring medical accessories Rechargeable toys 3 Description The BQ25123 is a highly int...

Page 2: ...lication Information 47 10 2 Typical Application 47 11 Layout 63 11 1 Layout Guidelines 63 11 2 Layout Example 63 12 Device and Documentation Support 64 12 1 Device Support 64 12 2 Receiving Notificat...

Page 3: ...y only mode the device can run from a battery up to 4 65 V A configurable load switch allows system optimization by disconnecting infrequently used devices The manual reset with timer allows mutliple...

Page 4: ...drain output that signals charging status and fault interrupts INT pulls low during charging INT is high impedance when charging is complete disabled or the charger is in high impedance mode When a f...

Page 5: ...he output filter cap from the buck converter to this ground as shown in the layout example PMID A3 B3 I O High Side Bypass Connection Connect at least 3 F of ceramic capacitance with DC bias derating...

Page 6: ...JS 001 1 2000 V Charged device model CDM per JEDEC specification JESD22 C101 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC...

Page 7: ...Mode PWM Not Switching V BUVLO V BAT 6 6 V 0 9 1 5 A 0 C TJ 60 C VIN 0 V or floating High Z Mode PWM Switching No Load 0 75 3 5 A 0 C TJ 85 C VIN 0 V High Z Mode PWM Switching LSLDO enabled 1 35 4 25...

Page 8: ...90 200 210 A I TERM Termination charge current Termination current programmable range over I2C 0 5 37 mA Termination current using IPRETERM I CHARGE 300 mA R ITERM 15 k 5 of ISET I CHARGE 300 mA R ITE...

Page 9: ...mA 20 I OCL_LDO Output current Limit LDO VLS LDO 0 V 275 365 475 mA I LS LDO Output current V VINLS 3 6 V VLSLDO 3 3 V 100 mA V VINLS 3 3 V VLSLDO 0 8 V 100 mA V VINLS 2 2 V VLSLDO 0 8 V 10 mA IIN LDO...

Page 10: ...N VUVLO 11 C tDGL_SHTDW N Deglitch time thermal shutdown TJ rising above TSHTDWN 4 s I2C INTERFACE I2C bus specification standard and fast mode frequency support 100 400 kHz VIL Input low threshold le...

Page 11: ...00 s LS LDO OUTPUT tON_LDO Turn ON time 100 mA load 500 s tOFF_LDO Turn OFF time 100 mA load 5 s PUSHBUTTON TIMER tWAKE1 Push button timer wake 1 Programmable range for wake1 function 0 08 1 s tWAKE2...

Page 12: ...T IQ Typical Start Up Timing and Operation VBAT VBUVLO Remove Battery Shows Charge Status VISET 3uA max 4uA max No SYS Load SYS Load Applied 3uA max 5uA max 4uA max nA of leakage with VIN present 0mA...

Page 13: ...eral ms SYS starts to rise Device enters Active Battery Mode after valid MR 1uA max User depresses button SYS is pulled down shortly after VBATUVLO is reached VBAT VBUVLO 3uA max Conditions SW_LDO 1 M...

Page 14: ...ture qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 D024 Figure 8 6 Blocking FET RDS ON vs Temperature Temperature qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0...

Page 15: ...vs Pre Charge Current Temperature qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 800 900 1000 D026 D024 VIN 5 V Figure 8 12 RDS ON of High Side MOSFET vs Temperature T...

Page 16: ...OOL SYS 1C 0 5C Disable Disable VBATREG 140mV LDO Load Switch Control IINLIM Q1 Q2 Q3 Q4 VIN_DPM VSUPPLY VBATREG LDO Control VSYSREG Thermal Shutdown Termination Reference IBAT VIN VINOVP VBAT VBATOVP...

Page 17: ...esent the device will enter Ship Mode upon removal of the supply The EN_SHIPMODE bit can be cleared using the I2C interface as well while the IN input is valid In addition to VIN VUVLO CD and MR must...

Page 18: ...attery Charge Disabled 9 3 3 Active Battery Only Connected When the battery above VBATUVLO is connected with no input source the battery discharge FET is turned on After the battery rises above VBATUV...

Page 19: ...V VBMON 98 VBMON 94 or 96 VBMON 90 or 92 VBMON 86 or 88 VBMON 84 D E C O D E R S3 S2 S1 S0 2 BAT TAP 4 BAT TAP 6 BAT TAP 8 BAT TAP 10 BAT TAP VREF 90 VB 80 VB 70 VB 60 VB VB 0 8 VBAT VBGUAGE_TH 2 0 F...

Page 20: ...it in the control register determines whether a charge cycle is initiated When the CE bit is 1 and a valid input source is connected the battery discharge FET is turned off and the output at SYS is re...

Page 21: ...gh an external resistor or through registers over I2C Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND The termination can be set between 5 and 20 of th...

Page 22: ...ernally programmed value the voltage at ISET reflects the actual charging current and can be used to monitor charge current The current out of ISET is 1 100 10 of the charge current The charge current...

Page 23: ...tery pack thermistor is monitored by the host Additionally the device provides a flexible voltage based TS input for monitoring the battery pack NTC thermistor The voltage at TS is monitored to determ...

Page 24: ...ol thresholds are not independently programmable The cool and warm NTC resistances for a selected resistor devider are calculated using Equation 3 and Equation 4 COOL COOL COOL LO HI COOL LO LO HI R x...

Page 25: ...ith an LED for visual indication The PG pin can be configured as a MR shifted MRS output when the PGB_MRS bit is set to 1 PG is high impedance when the MR input is not low and PG pulls to GND when the...

Page 26: ...PFM transition point where the part enters and exits Pulse Frequency Modulation to lower the power consumed at low loads the output voltage ripple and the efficiency The selected inductor must be sele...

Page 27: ...he device integrates a low Iq load switch which can also be used as a regulated output The LSCTRL pin can be used to turn the load on or off Activating LSCTRL continuously holds the switch in the on s...

Page 28: ...the host and the WAKE1 and or WAKE2 bits are updated on I2C The MR_WAKE bits and RESET FAULT bits are not cleared until the Push button Control Register is read from I2C When a MR reset condition is m...

Page 29: ...Status Condition Responses FAULT or STATUS ACTIONS CHARGER BEHAVIOR SYS BEHAVIOR LS LDO BEHAVIOR TS BEHAVIOR VIN_OV Update VIN_OV status Update STAT to fault interrupt on INT PG shown not good Disabl...

Page 30: ...state unless disabled in OTP or register settings FAULT A failure occurred The fault event must be cleared before going to the previous state DONE The termination requirements have been met VBAT is mo...

Page 31: ...mpatible interface to program and read many parameters I2C is a 2 wire serial interface developed by NXP The bus consists of a data line SDA and a clock line SCL with pull up structures When the bus i...

Page 32: ...ster ensures that data is valid A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse see Figure 9 8 All devices recognize the address sent by the...

Page 33: ...dressed slave All I2C compatible devices must recognize the STOP condition Upon the receipt of a STOP condition all devices know that the bus is released and wait for a START condition followed by a m...

Page 34: ...only B6 STAT_0 R x B5 EN_SHIPMODE Write Only 0 0 Normal Operation 1 Ship Mode Enabled B4 RESET_FAULT R x 1 RESET fault Indicates when the device meets the RESET conditions and is cleared after I2C re...

Page 35: ...one time Once read VIN_UV clears until the the UVLO event occurs B5 BAT_UVLO R x 1 BAT_UVLO fault BAT_UVLO continues to show fault after an I2C read as long as BAT_UVLO conditions exist B4 BAT_OCP R x...

Page 36: ...fault indicated and charge has stopped B3 EN_INT R W 1 0 Disable INT function INT only shows faults and does not show charge status 1 Enable INT function INT shows faults and charge status B2 WAKE_M R...

Page 37: ...mode ICHRG_RANGE and ICHRG bits are used to set the charge current The ICHRG is calculated using the following equation If ICHRG_RANGE is 0 then ICHRG 5 mA ICHRGCODE x 1 mA If ICHRG_RANGE is 1 then IC...

Page 38: ...he following equation If IPRETERM_RANGE is 0 then ITERM 500 A ITERMCODE x 500 A If IPRETERM_RANGE is 1 then ITERM 6 mA ITERMCODE x 1 mA If a value greater than 5 mA IPRETERM_RANGE 0 is written the set...

Page 39: ...ATREG is calculated using the following equation VBATREG 3 6 V VBREGCODE x 10 mV The charge voltage range is from 3 6 V to 4 65 V If a value greater than 4 65 V is written the setting goes to 4 65 V w...

Page 40: ...tep if SYS_SEL is 01 or 11 B1 SYS_VOUT_0 R W 0 OUT Voltage 100 mV step if SYS_SEL is 01 or 11 B0 LSB 0 SW_VOUT Bits Use SYS_SEL and SYS_VOUT bits to set the output on SYS The SYS voltage is calculated...

Page 41: ...0 2 V 10 0111 2 083 V 10 1000 2 167 V 10 1001 2 25 V 10 1010 2 333 V 10 1011 2 417 V 10 1100 2 5 V 10 1101 2 583 V 10 1110 2 667 V 10 1111 2 75 V 11 0000 1 8 V 11 0001 1 9 V 11 0010 2 V 11 0011 2 1 V...

Page 42: ...S_LDO_1 R W 1 LS LDO Voltage 200 mV B2 LS_LDO_0 R W 0 LS LDO Voltage 100 mV B1 0 B0 LSB MRRESET_VIN R W x 0 Reset sent when MR Reset time is met 1 Reset sent when MR Reset time is met and VUVLO VSLP V...

Page 43: ...0 0 After Reset device enters Ship mode 1 After Reset device enters Hi Z Mode B4 MRRESET_1 R W 1 MR Timer adjustment for reset 00 5 s 20 01 9 s 20 10 11 s 20 11 15 s 20 B3 MRRESET_0 R W 0 B2 PGB_MR R...

Page 44: ...ing the following equation I INLIM 50 mA I INLIM CODE x 50 mA The default may be overridden by the external resistor on ILIM 9 6 11 Voltage Based Battery Monitor Register Memory location 0x0Ah Reset S...

Page 45: ...ad then it will move to VBMON_RANGE 10 80 to 90 and continue until a non 000 value of VBMON_TH is found If this does not happen then VBMON_RANGE and VBMON_TH will be written with 00 000 The VBMON_READ...

Page 46: ...B5 VINDPM_1 R W 0 Input V IN_DPM voltage 200 mV B4 VINDPM_0 R W 0 Input V IN_DPM voltage 100 mV B3 2XTMR_EN R W 0 0 Timer is not slowed at any time 1 Timer is slowed by 2x when in any control other t...

Page 47: ...o shows the TS resistors which is also optional When powering up in default mode the battery voltage is the default for the part 4 2 V the SYS output is the default 1 8 V External resistors set the ch...

Page 48: ...he application diagram 10 2 2 1 Default Settings Connect ISET ILIM and IPRETERM pins to ground to program fast charge current to 10 mA input current limit to 100 mA and pre charge termination current...

Page 49: ...ermine that the battery is at a safe temperature during charging This device uses JEITA temperature profile which has four temperature thresholds Refer to Section 8 for the detailed thresholds number...

Page 50: ...mV div Figure 10 4 Entering DPPM Mode Time 4 ms div 10 mA div 100 mA div 2 V div 500 mV div Figure 10 5 Exiting DPPM Mode Time 4 ms div 20 mA div 100 mA div 2 V div 500 mV div Figure 10 6 Entering Bat...

Page 51: ...8 Charger On Off Using CD Time 4 ms div 10 mA div 20 mA div 2 V div 500 mV div Figure 10 9 OVP Fault www ti com BQ25123 SLUSCZ6A JANUARY 2018 REVISED MAY 2021 Copyright 2021 Texas Instruments Incorpo...

Page 52: ...Figure 10 12 1 8 VSYS System Efficiency Load Current A Efficiency 1E 6 1E 5 0 0001 0 001 0 01 0 10 2 0 5 40 50 60 70 80 90 100 D010 3 0 V BAT 3 6 V BAT 3 8 V BAT 4 2 V BAT TA 25 C VSYS 2 5 V Figure 1...

Page 53: ...T 4 2 V BAT TA 25 C VSYS 2 5 V Figure 10 18 2 5 VSYS Load Regulation Load Current A SYS Output Voltage V 1E 6 1E 5 0 0001 0 001 0 01 0 1 0 5 3 1845 3 2345 3 2845 3 3345 3 3845 D015 3 8 V BAT 4 2 V BAT...

Page 54: ...1 PA 10 PA 100 PA 1 mA 10 mA 100 mA 4 2 TA 25 C VSYS 3 3 V Figure 10 24 3 3 VSYS Line Regulation Load Current mA Frequency F SW kHz 0 50 100 150 200 250 300 0 200 400 600 800 1000 1200 1400 D023 5 V...

Page 55: ...tion Showing SW Time 400 ns div 500 mA div 200 mA div 2 V div 5 V div SW ILOAD 200 mA Figure 10 31 Light Load Operation Showing SW Time 400 ns div 500 mA div 200 mA div 2 V div 5 V div SW ILOAD 300 mA...

Page 56: ...nsient 0 to 50 mA Time 4 s div m 500 mA div 50 mV div 50 mV div 5 V div SW VSYS 3 3 V Figure 10 37 3 3 VSYS Load Transient 0 to 50 mA Time 4 s div m 500 mA div 200 mV div 50 mV div 5 V div SW VSYS 1 2...

Page 57: ...500 mA div 200 mV div 50 mV div 5 V div SW VSYS 3 3 V Figure 10 42 3 3 VSYS Load Transient 0 to 200 mA Time 1 ms div 1 V div 5 V div 2 V div Figure 10 43 Startup Showing SS on SYS in PWM Mode Time 20...

Page 58: ...Transient 0 to 10 mA Time 4 s div m 50 mV div 5 V div 20 mV div VSLSDO 1 2 V Figure 10 48 1 2 VLSLDO Load Transient 0 to 10 mA Time 4 s div m 50 mV div 5 V div 20 mV div VSLSDO 1 8 V Figure 10 49 1 8...

Page 59: ...nsient 0 to 100 mA Time 4 s div m 50 mV div 5 V div 100 mV div VSLSDO 1 8 V Figure 10 54 1 8 VLSLDO Load Transient 0 to 100 mA Time 4 s div m 50 mV div 5 V div 100 mV div VSLSDO 2 5 V Figure 10 55 2 5...

Page 60: ...rtup Showing SS on LS LDO in LDO Mode Time 20 ms div 200 mA div 2 V div 2 V div Figure 10 58 Short Circuit and Recovery for LDO BQ25123 SLUSCZ6A JANUARY 2018 REVISED MAY 2021 www ti com 60 Submit Docu...

Page 61: ...PG Functions as Shifted MR Output Time 400 s div m 500 mV div 2 V div 2 V div 5 V div Figure 10 62 PG Functions as Shifted MR Output Time 200 ms div 2 V div 2 V div 500 mV div 2 V div Wake1 500 ms Wa...

Page 62: ...igure 10 67 RESET Timing Time 2 s div 2 V div 2 V div 500 mV div 2 V div Figure 10 68 RESET Timing and Enter Ship Mode Power Supply Recommendations It is recommended to use a power supply that is capa...

Page 63: ...e Place the bypass caps for PMID SYS and LSLDO close to the pins Place the GNDs of the PMID and IN caps close to each other Do not route so the power planes are interrupted 11 2 Layout Example Figure...

Page 64: ...essarily reflect TI s views see TI s Terms of Use 12 4 Trademarks TI E2E is a trademark of Texas Instruments All trademarks are the property of their respective owners 12 5 Electrostatic Discharge Cau...

Page 65: ...m threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard cla...

Page 66: ...PACKAGE OPTION ADDENDUM www ti com 6 Jun 2021 Addendum Page 2...

Page 67: ...ins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant BQ25123YFPR DSBGA YFP 25 3000 180 0 8 4 2 65 2 65 0 69 4 0 8 0 Q1 BQ25123YFPT DSBGA YFP 25 250 180 0 8 4 2 65 2 65...

Page 68: ...Package Type Package Drawing Pins SPQ Length mm Width mm Height mm BQ25123YFPR DSBGA YFP 25 3000 182 0 182 0 20 0 BQ25123YFPT DSBGA YFP 25 250 182 0 182 0 20 0 PACKAGE MATERIALS INFORMATION www ti co...

Page 69: ...BALL GRID ARRAY NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change...

Page 70: ...nal dimensions may vary due to manufacturing tolerance considerations and also routing constraints See Texas Instruments Literature No SNVA009 www ti com lit snva009 SOLDER MASK DETAILS NOT TO SCALE S...

Page 71: ...9 2019 DSBGA 0 5 mm max height YFP0025 DIE SIZE BALL GRID ARRAY NOTES continued 4 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release SYMM SYMM SOLDER PAS...

Page 72: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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