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CS

SCLK

SDI

SDO

DAISY

ADS8694
ADS8698

CS

SCLK

SDO

SDI

H

o

s

t

C

o

n

tr

o

lle

r

RST / PD

RST / PD

SDO

N

(from previous device)

or DGND

ADS8694, ADS8698

SBAS686 – JULY 2015

8.4 Device Functional Modes

8.4.1 Device Interface

8.4.1.1 Digital Pin Description

The digital data interface for the ADS8694 and ADS8698 is shown in

Figure 73. Pin Configuration for the Digital Interface

The signals shown in

are summarized as follows:

8.4.1.1.1

CS (Input)

CS indicates an active-low, chip-select signal. CS is also used as a control signal to trigger a conversion on the
falling edge. Each data frame begins with the falling edge of the CS signal. The analog input channel to be
converted during a particular frame is selected in the previous frame. On the CS falling edge, the devices sample
the input signal from the selected channel and a conversion is initiated using the internal clock. The device
settings for the next data frame can be input during this conversion process. When the CS signal is high, the
ADC is considered to be in an idle state.

8.4.1.1.2

SCLK (Input)

This pin indicates the external clock input for the data interface. All synchronous accesses to the device are
timed with respect to the falling edges of the SCLK signal.

8.4.1.1.3

SDI (Input)

SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for
device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line
are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made
to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of
the CS signal.

8.4.1.1.4

SDO (Output)

SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data
output frame varies depending on the register setting for the SDO format; see

. A low level on CS

releases the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the
output data stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits
on every falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z
state when CS goes high.

34

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Copyright © 2015, Texas Instruments Incorporated

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Summary of Contents for ADS869 Series

Page 1: ... of Input Overvoltage Protection Up to 20 V 500 kSPS The devices feature integrated analog On Chip 4 096 V Reference with Low Drift front end circuitry for each input channel with Excellent Performance overvoltage protection up to 20 V a 4 or 8 channel multiplexer with automatic and manual scanning 500 kSPS Aggregate Throughput modes and an on chip 4 096 V reference with low DNL 0 5 LSB INL 1 5 LS...

Page 2: ... 5 12 Device and Documentation Support 69 7 3 Recommended Operating Conditions 5 12 1 Documentation Support 69 7 4 Thermal Information 5 12 2 Related Links 69 7 5 Electrical Characteristics 6 12 3 Community Resources 69 7 6 Timing Requirements Serial Interface 10 12 4 Trademarks 69 7 7 Typical Characteristics 11 12 5 Electrostatic Discharge Caution 69 8 Detailed Description 20 12 6 Glossary 69 8 1...

Page 3: ...l communication Active low logic input 2 RST PD Digital input Dual functionality to reset or power down the device 3 DAISY Digital input Chain the data input during serial communication in daisy chain mode Active low logic input to enable the internal reference When low the internal reference is enabled 4 REFSEL Digital input REFIO becomes an output that includes the VREF voltage When high the int...

Page 4: ...nalog input channel 3 negative input Decouple with AIN_3P on pin 23 23 AIN_3P Analog input Analog input channel 3 positive input Decouple with AIN_3GND on pin 22 Analog input channel 4 negative input Decouple with AIN_4P on pin 25 24 NC AIN_4GND Analog input No connection for the ADS8694 this pin can be left floating or connected to AGND Analog input channel 4 positive input Decouple with AIN_4GND...

Page 5: ... AIN_nP AIN_nGND Human body model HBM per ANSI ESDA JEDEC JS 001 1 Electrostatic V ESD V discharge All other pins 2000 Charged device model CDM per JEDEC specification JESD22 C101 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control proces...

Page 6: ...ut At TA 25 C zi Input impedance 0 85 1 1 15 MΩ B all input ranges Input impedance drift All input ranges 7 25 ppm C B VIN 2 25 With voltage at AIN_nP pin VIN A input range 2 5 VREF RIN VIN 2 00 With voltage at AIN_nP pin VIN A input range 1 25 VREF RIN VIN 1 60 With voltage at AIN_nP pin VIN IIkg in Input leakage current µA A input range 0 625 VREF RIN VIN 2 50 With voltage at AIN_nP pin VIN A in...

Page 7: ... 6 At TA 25 C 0 5 1 A input range 1 25 VREF At TA 25 C EO Offset error 0 5 1 5 mV A input range 0 625 VREF At TA 25 C 0 5 2 A input range 0 to 2 5 VREF At TA 25 C 0 5 2 A input range 0 to 1 25 VREF At TA 25 C 0 5 1 A input range 2 5 VREF 6 At TA 25 C 0 5 1 A input range 1 25 VREF Offset error matching At TA 25 C 0 5 1 5 mV A channel to channel input range 0 625 VREF At TA 25 C 0 5 2 A input range ...

Page 8: ...ignal bandwidth 0 1 dB At TA 25 C all input ranges 2 5 kHz B AUXILIARY CHANNEL Resolution 16 Bits A V AUX_IN AUX_IN voltage range AUX_IN AUX_GND 0 VREF V A AUX_IN 0 VREF V A Operating input range AUX_GND 0 V A During sampling 75 pF C Ci Input capacitance During conversion 5 pF C IIkg in Input leakage current 100 nA A DNL Differential nonlinearity 0 99 0 6 1 5 LSB A INL Integral nonlinearity 4 1 5 ...

Page 9: ...specified 2 7 3 3 5 25 B performance For the ADS8698 AVDD 5 V fS 13 16 A maximum and internal reference Dynamic IAVDD_DYN mA AVDD For the ADS8694 AVDD 5 V fS 8 5 11 5 A maximum and internal reference For the ADS8698 AVDD 5 V device not converting and internal 10 12 A reference IAVDD_STC Analog supply current Static mA For the ADS8694 AVDD 5 V device not converting and internal 5 5 8 5 A reference ...

Page 10: ... 2 µs fSCLK Serial clock frequency fS max 18 MHz tSCLK Serial clock time period fS max 56 ns tCONV Conversion time 825 ns tDZ_CSDO Delay time CS falling to data enable 10 ns tD_CKCS Delay time last SCLK falling to CS rising 10 ns tDZ_CSDO Delay time CS rising to SDO going to 3 state 10 ns TIMING REQUIREMENTS tACQ Acquisition time 1175 ns tPH_CK Clock high time 0 4 0 6 tSCLK tPL_CK Clock low time 0...

Page 11: ...15 9 3 3 9 15 10 6 2 2 6 10 Analog Input Current µA Input Voltage V C002 250C 400C 1250C ADS8694 ADS8698 www ti com SBAS686 JULY 2015 7 7 Typical Characteristics At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Input range 2 5 VREF Figure 3 Input Current vs Temperature Figure 2 Input I V Characteristic Number of samples 1160 Figure 4 Input Im...

Page 12: ...utput Codes C010 ADS8694 ADS8698 SBAS686 JULY 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Mean 131072 3 sigma 2 76 input 0 V Mean 131072 3 sigma 2 42 input 1 25 VREF range 0 625 VREF range 2 5 VREF Figure 8 DC Histogram for Mid Scale Inputs 0 625 VREF Figure 9 DC Histogram for Mid Scale I...

Page 13: ...0 0 5 1 1 5 2 0 65536 131072 196608 262144 Integral Nonlinearity LSB Codes LSB C016 ADS8694 ADS8698 www ti com SBAS686 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 1 25 VREF Range 0 625 VREF Figure 14 Typical INL for All Codes Figure 15 Typical INL for All Codes Range 2 5 VREF Range 1 25 V...

Page 14: ...0 Maximum Minimum 2 1 0 1 2 40 7 26 59 92 125 Integral Nonlinearity LSB Free Air Temperature oC C021 Maximum Minimum ADS8694 ADS8698 SBAS686 JULY 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Range 0 625 VREF Figure 21 INL vs Temperature 2 5 VREF Figure 20 INL vs Temperature ...

Page 15: ...VREF 0 625 VREF 2 5 VREF 1 25 VREF ADS8694 ADS8698 www ti com SBAS686 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Figure 26 Gain Error vs Temperature Across Input Ranges Figure 27 Typical Histogram for Gain Error Drift Range 2 5 VREF Figure 28 Gain Error vs Temperature Across Cha...

Page 16: ... 80 40 0 0 50000 100000 150000 200000 250000 Amplitude dB Input Frequency Hz C034 ADS8694 ADS8698 SBAS686 JULY 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Number of points 64k fIN 1 kHz SNR 90 6dB Number of points 64k fIN 1 kHz SNR 91 83 dB SINAD 90 45dB THD 106dB SFDR 109 dB SINAD 91 73 ...

Page 17: ...rmonic Distortion dB Input Frequency Hz C040 2 5 VREF 1 25 VREF 0 625 VREF 2 5 VREF 1 25 VREF 88 89 90 91 92 93 94 95 40 7 26 59 92 125 Signal to Noise Distortion Ratio dB Free Air Temperature oC C039 2 5 VREF 1 25 VREF 0 625 VREF 2 5 VREF 1 25 VREF ADS8694 ADS8698 www ti com SBAS686 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPL...

Page 18: ...mic mA Free Air Temperature oC C058 ADS8694 ADS8698 SBAS686 JULY 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Input 2 maximum input voltage Figure 45 AVDD Current vs Temperature for the ADS8698 Figure 44 Isolation Crosstalk vs Frequency for fS 500 kSPS Overrange Inputs Figure 47 AVDD Curre...

Page 19: ...LY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Figure 50 AVDD Current vs Temperature Power Down Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links ADS8694 ADS8698 ...

Page 20: ...circuit a programmable gain amplifier PGA and a second order antialiasing filter that conditions the input signal before being fed into a 4 or 8 channel analog multiplexer MUX The output of the MUX is digitized using a 18 bit analog to digital converter ADC based on the successive approximation register SAR architecture This overall system can achieve a maximum throughput of 500 kSPS combined acro...

Page 21: ...w a 0 1 V range on the AIN_nGND pin for all analog input channels This feature is useful in modular systems where the sensor or signal conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible In such cases running separate wires from the AIN_nGND pin of the device to the sensor or ...

Page 22: ...ltage AVDD 5 V or offers a low impedance of 30 kΩ the internal overvoltage protection circuit can withstand up to 20 V on the analog input pins Table 1 Input Overvoltage Protection Limits When AVDD 5 V or Offers a Low Impedance of 30 kΩ 1 INPUT CONDITION TEST ADC COMMENTS VOVP 20 V CONDITION OUTPUT All input VIN VRANGE Within operating range Valid Device functions as per data sheet specifications ...

Page 23: ...Overvoltage Protection Limits When AVDD Floating with Impedance 30 kΩ 1 INPUT CONDITION TEST ADC OUTPUT COMMENTS VOVP 11 V CONDITION Device is not functional but is protected internally by VIN VOVP Within overvoltage range All input ranges Invalid the OVP circuit This usage condition may cause irreversible damage VIN VOVP Beyond overvoltage range All input ranges Invalid to the device 1 AVDD float...

Page 24: ...T 2 BIT 1 BIT 0 2 5 VREF 0 0 0 0 1 25 VREF 0 0 0 1 0 625 VREF 0 0 1 0 0 to 2 5 VREF 0 1 0 1 0 to 1 25 VREF 0 1 1 0 8 3 5 Second Order Low Pass Filter LPF In order to mitigate the noise of the front end amplifiers and gain resistors of the PGA each analog input channel of the ADS8694 and ADS8698 features a second order antialiasing LPF at the output of the PGA The magnitude and phase response of th...

Page 25: ...l Registers section The devices automatically scan only the selected analog inputs in ascending order The maximum overall throughput for the ADS8694 and ADS8698 is specified at 500 kSPS across all channels The per channel throughput is dependent on the number of channels selected in the multiplexer scanning sequence For example the throughput per channel is equal to 250 kSPS if only two channels a...

Page 26: ...ternal band gap circuit creates a low pass filter with this capacitor to band limit the noise of the reference The use of a smaller capacitor value allows higher reference noise in the system thus degrading SNR and SINAD performance Do not use the REFIO pin to drive external ac or dc loads because REFIO has limited current output capability The REFIO pin can be used as a source if followed by a su...

Page 27: ...n in Figure 59 Although all tested units exhibit a positive shift in their output voltages negative shifts are also possible Note that the histogram in Figure 59 shows the typical shift for exposure to a single reflow profile Exposure to multiple reflows which is common on PCBs with surface mount components on both sides causes additional shifts in the output voltage If the PCB is to be exposed to...

Page 28: ...this mode because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin which is internally connected to the ADC reference input The output of the external reference must be appropriately filtered to minimize the resulting effect of the reference noise on system performance A typical connection diagram for this mode is shown in Figure 62 Figure 62 Device Connect...

Page 29: ...rovides direct interface to an internal high precision 16 bit ADC through the multiplexer because this channel does not include the front end analog signal conditioning that the other analog input channels have The AUX channel supports a single unipolar input range of 0 V to VREF because there is no front end PGA The input signal on the AUX_IN pin can vary from 0 V to VREF whereas the AUX_GND pin ...

Page 30: ...50 ADS8694 ADS8698 SBAS686 JULY 2015 www ti com The AUX channel in the ADS8694 and ADS8698 offers a true 16 bit performance with no missing codes Some typical performance characteristics of the AUX channel are shown in Figure 65 to Figure 68 Mean 32767 15 sigma 0 83 AUX channel Figure 65 DC Histogram for Mid Scale Input Figure 66 Offset and Gain vs Temperature AUX Channel AUX Channel fIN 1 kHz fIN...

Page 31: ...inimizes the harmonic distortion at higher input frequencies In general the amplifier bandwidth requirements can be calculated on the basis of Equation 1 where f 3dB is the 3 dB bandwidth of the RC filter 1 Distortion In order to achieve the distortion performance of the AUX channel the distortion of the input driver must be at least 10 dB lower than the specified distortion of the internal ADC as...

Page 32: ...he difference between the positive full scale PFS input voltage and the negative full scale NFS input voltage The LSB size is equal to FSR 218 FSR 262144 because the resolution of the ADC is 18 bits For a reference voltage of VREF 4 096 V the LSB values corresponding to the different input ranges are listed in Table 4 Figure 69 18 Bit ADC Transfer Function Straight Binary Format Table 4 ADC LSB Va...

Page 33: ... high alarm threshold T hysteresis H The alarm resets when the digital output for the channel is less than or equal to the high alarm lower limit high alarm T H 2 This function is shown in Figure 70 Similarly the lower alarm is triggered when the digital output for a particular channel falls below the low alarm lower limit low alarm threshold T H 1 The alarm resets when the digital output for the ...

Page 34: ...t for the data interface All synchronous accesses to the device are timed with respect to the falling edges of the SCLK signal 8 4 1 1 3 SDI Input SDI is the serial data input line SDI is used by the host processor to program the internal device registers for device configuration At the beginning of each data frame the CS signal goes low and the data on the SDI line are read by the device at every...

Page 35: ... PWR_DN mode and the program registers are reset to default tPL_RST_PD 400 ns value The devices can be placed into power down PWR_DN mode by pulling the RST PD pin to a logic low state for at least 400 ns The RST PD pin is asynchronous to the clock thus RST PD can be triggered at any time regardless of the status of other pins including the analog input channels When the device is in power down mo...

Page 36: ...DO until the 16th falling edge appears on the SCLK input Because the ADC conversion time is fixed the maximum value is given in the Electrical Characteristics table the 16th SCLK falling edge must appear after the internal conversion is over otherwise data output from the device is incorrect Therefore the SCLK frequency cannot exceed a maximum value as provided in the Timing Requirements Serial In...

Page 37: ...At the falling edge of the CS signal all devices sample the input signal at their respective selected channels and enter into conversion phase For the first 16 SCLK cycles the internal register settings for the next conversion can be entered using the SDI line that is common to all devices in the chain During this time period the SDO outputs for all devices remain low At the end of conversion ever...

Page 38: ...trolled by separate CS control lines from the host controller Figure 78 Star Topology Connection Schematic The timing diagram for a typical data frame in the star topology is the same as in a stand alone device operation as illustrated in Figure 75 The data frame for a particular device starts with the falling edge of the CS signal and ends when the CS signal goes high Because the host controller ...

Page 39: ...erent modes of the device After power up the program registers wake up with the default values and require appropriate configuration settings before performing any conversion The diagram in Figure 79 explains how to switch the device from one mode of operation to another Figure 79 State Transition Diagram 8 4 2 1 Continued Operation in the Selected Mode NO_OP Holding the SDI line low continuously ...

Page 40: ...gnal on the previously selected channel 8 4 2 3 STANDBY Mode STDBY The devices support a low power standby mode STDBY in which only part of the circuit is powered down The internal reference and buffer is not powered down and therefore the devices can be quickly powered up in 20 µs on exiting the STDBY mode When the device comes out of STDBY mode the program registers are not reset to the default ...

Page 41: ... CS falling edge the device samples the analog input at the channel selected by the MAN_CH_n command or the first channel of the AUTO_RST mode sequence To ensure that the input signal is sampled correctly keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device internal circuitry can be fully powered up and biased properly before taking the sample The data output for...

Page 42: ...are power down To enter PWR_DN mode using software execute a valid write operation on the command register with a software PWR_DN command of 8300h as shown in Figure 82 The command is executed and the device enters PWR_DN mode on the next CS rising edge following this write operation The device remains in PWR_DN mode if no valid conversion command AUTO_RST or MAN_Ch_n is executed and SDI remains l...

Page 43: ...lete frame of 34 SCLK cycles The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control register 01h to 02h in the program register see the Program Register Map section In this mode the devices continuously cycle through the selected channels in ascending order beginning with the lowest channel and converting all channels selected in the program register ...

Page 44: ...can be pulled high immediately after the MAN_Ch_n command or after reading the output data of the frame However in order to accurately acquire and convert the input signal on the next channel the command frame must be a complete frame of 34 SCLK cycles See Table 6 for a list of commands to select individual channels during MAN_Ch_n mode Figure 86 Enter MAN_Ch_n Scan Mode Timing Diagram The manual ...

Page 45: ...n automatic scan using the AUTO_RST command When the reset command is received the ongoing auto mode sequence is reset and restarts from the lowest selected channel in the sequence In MAN_Ch_n mode the same input channel is selected during every data conversion frame The input command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6 If a particular input channel is...

Page 46: ...h as shown in Figure 90 The device remains in RST mode if no valid conversion command AUTO_RST or MAN_Ch_n is executed and SDI remains low see the Continued Operation in the Selected Mode NO_OP section during the subsequent data frames When the device operates in RST mode the program register settings can be updated as explained in the Program Register Read Write Operation section using 16 SCLK cy...

Page 47: ...a frame when the CS signal goes high Table 6 Command Register Map MSB BYTE LSB BYTE COMMAND REGISTER OPERATION IN NEXT FRAME Hex B15 B14 B13 B12 B11 B10 B9 B8 B 7 0 Continued Operation 0 0 0 0 0 0 0 0 0000 0000 0000h Continue operation in previous mode NO_OP Standby 1 0 0 0 0 0 1 0 0000 0000 8200h Device is placed into standby mode STDBY Power Down 1 0 0 0 0 0 1 1 0000 0000 8300h Device is powered...

Page 48: ...r Read Write Operation The program register is a 16 bit read or write register There must be a minimum of 24 SCLKs after the CS falling edge for any read or write operation to the program registers When CS goes low the SDO line goes low as well The device receives the command see Table 7 and Table 8 through SDI where the first seven bits bits 15 9 represent the register address and the eighth bit ...

Page 49: ...the 8 bit data from the addressed register during the next eight clocks in MSB first fashion A typical timing diagram for a program register read cycle is shown in Figure 92 Table 8 Read Cycle Command Word REGISTER ADDRESS WR RD DATA PIN Bits 15 9 Bit 8 Bits 7 0 SDI ADDR 6 0 0 XXXXX SDO 0000 000 0 DOUT 7 0 Figure 92 Program Register Read Cycle Timing Diagram Copyright 2015 Texas Instruments Incorp...

Page 50: ...Flag Ch2 Flag Ch1 Flag Ch0 Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm ALARM Ch 0 3 Tripped Flag 11h 00h Flag Ch0 Low Flag Ch0 High Flag Ch1 Low Flag Ch1 High Flag Ch2 Low Flag Ch2 High Flag Ch3 Low Flag Ch3 High Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm ALARM Ch 0 3 Ac...

Page 51: ...8h 00h CH0_LT 15 8 Ch 0 Low Threshold LSB 19h 00h CH0_LT 7 0 See the Alarm Threshold Setting Registers for details regarding the ALARM threshold settings registers Ch 7 Hysteresis 38h 00h CH7_HYST 7 0 Ch 7 High Threshold MSB 39h FFh CH7_HT 15 8 Ch 7 High Threshold LSB 3Ah FFh CH7_HT 7 0 Ch 7 Low Threshold MSB 3Bh 00h CH7_LT 15 8 Ch 7 Low Threshold LSB 3Ch 00h CH7_LT 7 0 COMMAND READ BACK Read Only...

Page 52: ...r A read operation on any of these bits or registers outputs all 1 s on the SDO line Table 10 AUTO_SEQ_EN Field Descriptions Bit Field Type Reset Description 7 CH7_EN R W 1h Channel 7 enable 0 Channel 7 is not selected for sequencing in AUTO_RST mode 1 Channel 7 is selected for sequencing in AUTO_RST mode 6 CH6_EN R W 1h Channel 6 enable 0 Channel 6 is not selected for sequencing in AUTO_RST mode ...

Page 53: ... can be included in the AUTO_RST sequence 1 The analog front end on channel 6 is powered down and channel 6 cannot be included in the AUTO_RST sequence 5 CH5_PD R W 0h Channel 5 power down 0 The analog front end on channel 5 is powered up and channel 5 can be included in the AUTO_RST sequence 1 The analog front end on channel 5 is powered down and channel 5 cannot be included in the AUTO_RST seque...

Page 54: ...4 3 BITS 2 0 16th SCLK falling edge Conversion result for selected 000 SDO pulled low no latency channel MSB first 16th SCLK falling edge Conversion result for selected Channel 001 SDO pulled low no latency channel MSB first address 1 16th SCLK falling edge Conversion result for selected Channel Device SDO pulled 010 no latency channel MSB first address 1 address 1 low 16th SCLK falling edge Conve...

Page 55: ... these registers is 00h Figure 96 Channel n Input Range Registers 7 6 5 4 3 2 1 0 0 0 0 0 Range_CHn 3 0 R 0h R 0h R 0h R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 15 Channel n Input Range Registers Field Descriptions Bit Field Type Reset Description 7 4 0 R 0h Must always be set to 0 3 0 Range_CHn 3 0 R W 0h Input range selection bits for channel n n 0 to 3 for the ADS8...

Page 56: ...arm Tripped Alarm Tripped Alarm Flag Ch7 1 Flag Ch6 Flag Ch5 Flag Ch4 Flag Ch3 Flag Ch2 Flag Ch1 Flag Ch0 R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R Read only n value after reset 1 Shading indicates bits or registers that are not included in the 4 channel version of the device A write operation on any of these bits or registers has no effect on device behavior A read operation on any of thes...

Page 57: ...m Active Alarm Active Alarm Active Alarm Flag Ch0 Low Flag Ch0 High Flag Ch1 Low Flag Ch1 High Flag Ch2 Low Flag Ch2 High Flag Ch3 Low Flag Ch3 High R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R Read only n value after reset Table 18 ALARM Ch0 3 Active Flag Register Field Descriptions Bit Field Type Reset Description 7 0 Active Alarm Flag Ch n Low R 0h Active alarm flag high low for channel n n...

Page 58: ...channel version of the device A write operation on this register has no effect on device behavior A read operation on this register outputs all 1 s on the SDO line Table 20 ALARM Ch4 7 Active Flag Register Field Descriptions Bit Field Type Reset Description 7 0 Active Alarm Flag Ch n Low R 0h Active alarm flag high low for channel n n 4 to 7 or High n 4 to 7 Each individual bit indicates an active...

Page 59: ...15 8 Ch 2 Low Threshold LSB 23h CH2_LT 7 0 Ch 3 Hysteresis 24h CH3_HYST 7 0 Ch 3 High Threshold MSB 25h CH3_HT 15 8 Ch 3 High Threshold LSB 26h CH3_HT 7 0 Ch 3 Low Threshold MSB 27h CH3_LT 15 8 Ch 3 Low Threshold LSB 28h CH3_LT 7 0 Ch 4 Hysteresis 1 29h CH4_HYST 7 0 Ch 4 High Threshold MSB 2Ah CH4_HT 15 8 Ch 4 High Threshold LSB 2Bh CH4_HT 7 0 Ch 4 Low Threshold MSB 2Ch CH4_LT 15 8 Ch 4 Low Thresh...

Page 60: ... n High Threshold MSB Registers 7 6 5 4 3 2 1 0 CHn_HT 15 8 R W 1h LEGEND R W Read Write n value after reset Table 22 Channel n High Threshold MSB Register Field Descriptions n 0 to 7 for the ADS8698 n 0 to 3 for the ADS8694 Bit Field Type Reset Description 7 0 CHn_HT 15 8 R W 1h These bits set the MSB byte for the 16 bit channel n high alarm n 0 to 7 for the ADS8698 For example bits 7 0 of the ch...

Page 61: ...0 0010 to 1111 1110 LSB byte is 02h to FEh 1111 1111 LSB byte is FFh Figure 105 Ch n Low Threshold MSB Registers 7 6 5 4 3 2 1 0 CHn_LT 15 8 R W 0h LEGEND R W Read Write n value after reset Table 24 Channel n Low Threshold MSB Register Field Descriptions n 0 to 7 for the ADS8698 n 0 to 3 for the ADS8694 Bit Field Type Reset Description 7 0 CHn_LT 15 8 R W 0h These bits set the MSB byte for the 16 ...

Page 62: ...01 LSB byte is 01h 0000 0010 to 1110 1111 LSB byte is 02h to FEh 1111 1111 LSB byte is FFh 8 5 2 3 6 Command Read Back Register address 3Fh This register allows the device mode of operation to be read On execution of this command the device outputs the command word executed in the previous data frame The output of the command register appears on SDO from the 16th falling edge onwards in an MSB fir...

Page 63: ... include an integrated analog front end for each input channel and an integrated precision reference with a buffer As such this device family does not require any additional external circuits for driving the reference or analog input pins of the ADC 9 2 Typical Applications 9 2 1 Phase Compensated 8 Channel Multiplexed Data Acquisition System for Power Automation Figure 108 8 Channel Multiplexed D...

Page 64: ...mum latency in data output resulting from the SAR architecture The integration offered by this device makes the ADS8694 and ADS8698 an ideal selection for such applications because the integrated signal conditioning helps minimize system components and avoids the need for generating high voltage supply rails The overall system level dc precision gain and offset errors and low temperature drift off...

Page 65: ... are given below Up to eight channels of user programmable inputs Voltage inputs with a typical ZIN of 1 MΩ 10 V 5 V 2 5 V 0 V to 10 V and 0 V to 5 V Current inputs with a ZIN of 300 Ω 0 mA to 20 mA 4 mA to 20 mA and 20 mA A 18 bit SAR ADC with SPI Accuracy of 0 2 at 25 C over the entire input range of voltage and current inputs Onboard isolated Fly Buck power supply with inrush current protection...

Page 66: ...SD diodes The RC low pass mode filters are used on each analog input before the input reaches the ADS8698 thus eliminating any high frequency noise pickups and minimizing aliasing For a step by step design procedure circuit schematics bill of materials PCB files simulation results and test results see 16 Bit 8 Channel Integrated Analog Input Module for Programmable Logic Controllers PLCs TIDU365 1...

Page 67: ...the bypass capacitors must be avoided All ground pins must be connected to the ground plane using short low impedance paths There are two decoupling capacitors used for the REFCAP pin The first is a small 1 μF X7R grade 0603 size ceramic capacitor placed close to the device pins for decoupling the high frequency signals and the second is a 22 µF X7R grade 1210 size ceramic capacitor to provide the...

Page 68: ...D 25 AIN_4P 24 AIN_4GND 23 AIN_3P 22 AIN_3GND 21 AIN_2P 20 AIN_2GND 1µF 22µF GND GND GND GND GND 10µF GND 1µF GND CS SCLK SDO SDI RST PD REFSEL DAISY Optional RC Filter for Channel AIN_0 to AIN_7 1µF Digital Pins Analog Pins 10µF When using internal VREF ADS8694 ADS8698 SBAS686 JULY 2015 www ti com 11 2 Layout Example Figure 112 Board Layout for the ADS8694 and ADS8698 68 Submit Documentation Feed...

Page 69: ...specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Online Community TI s Engineer to Engineer E2E Community Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers Design Support TI s Design Support Quickly find helpful E2E forums along with design support tool...

Page 70: ...nformation This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation 70 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links ADS8694 ADS8698 ...

Page 71: ...le for use in specified lead free processes TI may reference these types of products as Pb Free RoHS Exempt TI defines RoHS Exempt to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption Green TI defines Green to mean the content of Chlorine Cl and Bromine Br based flame retardants meet JS709B low halogen requirements of 1000ppm threshold Antimony...

Page 72: ...ing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis ...

Page 73: ...s SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant ADS8694IDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 ADS8698IDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 21 Jul 2015 Pack Materials Page 1 ...

Page 74: ...Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS8694IDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 ADS8698IDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 PACKAGE MATERIALS INFORMATION www ti com 21 Jul 2015 Pack Materials Page 2 ...

Page 75: ...ers Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change without notice 3 This dimension does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15 mm per side 4 This dimension does not include interlead flash Interlead flash shall not exceed 0 25 mm per side 5 Ref...

Page 76: ...PC 7351 may have alternate designs 7 Solder mask tolerances between and around signal pads can vary based on board fabrication site LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE 10X SYMM SYMM 1 19 20 38 15 000 METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK DETAILS NON SOLDER MASK DEFINED PREFERRED SOLDER MASK DEFINED 4220221 A 05 2020...

Page 77: ...continued 8 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations 9 Board assembly site may have different recommendations for stencil design SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL SCALE 10X SYMM SYMM 1 19 20 38 4220221 A 05 2020 ...

Page 78: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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