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±
20
±
12
±
4
4
12
20
±
20
±
12
±
4
4
12
20
A
n
a
lo
g
I
n
p
u
t
C
u
rr
e
n
t
(µ
A
)
Input Voltage (V)
C004
±
30
±
20
±
10
0
10
20
30
±
30
±
20
±
10
0
10
20
30
A
n
a
lo
g
I
n
p
u
t
C
u
rr
e
n
t
(µ
A
)
Input Voltage (V)
C003
-----
± 2.5 VREF
-----
± 1.25 VREF
----- ± 0.625 VREF
------ +2.5 VREF
------+1.25VREF
SBAS686 – JULY 2015
shows the voltage versus current response of the internal overvoltage protection circuit when the
device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input
pins is limited by the 1-M
Ω
input impedance. However, for voltages beyond ±20 V, the internal node voltages
surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the
input pins.
The same overvoltage protection circuit also provides protection to the device when the device is not powered on
and AVDD is floating with an impedance > 30 k
Ω
. This condition can arise when the input signals are applied
before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in
Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 k
Ω
(1)
INPUT CONDITION
TEST
ADC OUTPUT
COMMENTS
(V
OVP
= ±11 V)
CONDITION
Device is not functional but is protected internally by
|V
IN
| < |V
OVP
|
Within overvoltage range
All input ranges
Invalid
the OVP circuit.
This usage condition may cause irreversible damage
|V
IN
| > |V
OVP
|
Beyond overvoltage range
All input ranges
Invalid
to the device.
(1)
AVDD = floating, GND = 0, AIN_
n
GND = 0 V, |V
RANGE
| is the maximum input voltage for any selected input range, and |V
OVP
| is the
break-down voltage for the internal OVP circuit. Assume that R
S
is approximately 0.
shows the voltage versus current response of the internal overvoltage protection circuit when the
device is not powered on. According to this I-V response, the current flowing into the device input pins is limited
by the 1-M
Ω
input impedance. However, for voltages beyond ±11 V, the internal node voltages surpass the
break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.
Figure 53. I-V Curve for an Input OVP Circuit
Figure 54. I-V Curve for an Input OVP Circuit
(AVDD = 5 V)
(AVDD = Floating)
Copyright © 2015, Texas Instruments Incorporated
23
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