Tews Technologies TPMC682-10 User Manual Download

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TPMC682 User Manual Issue 1.1

Page 5 of 36

Table of Figures

FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6

FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7

FIGURE 3-1 : INPUT TRANSFER TIMING DIAGRAM .....................................................................................9

FIGURE 3-2 : OUTPUT TRANSFER TIMING DIAGRAM...............................................................................10

FIGURE 4-1 : PCI9030 LOCAL SPACE CONFIGURATION ..........................................................................11

FIGURE 4-2 : CONTROL REGISTER SPACE ...............................................................................................12

FIGURE 4-3 : INTERRUPT AND FIFO CONTROL REGISTER (IFCR) .........................................................13

FIGURE 4-4 : PORT DATA DIRECTION REGISTER (PDDR) .......................................................................13

FIGURE 4-5 : HANDSHAKE STATUS AND CONTROL REGISTER 2 (HSCR2) ..........................................14

FIGURE 4-6 : HANDSHAKE STATUS AND CONTROL REGISTER 1 (HSCR1) ..........................................15

FIGURE 4-7 : HANDSHAKE STATUS AND CONTROL REGISTER 0 (HSCR0) ..........................................16

FIGURE 4-8 : FIFO THRESHOLD REGISTER 2 (FTHR2).............................................................................17

FIGURE 4-9 : FIFO THRESHOLD REGISTER 1 (FTHR1).............................................................................17

FIGURE 4-10: FIFO THRESHOLD REGISTER 0 (FTHR0)............................................................................17

FIGURE 4-11: FIFO DATA COUNTER REGISTER 2 (FDCR2) .....................................................................18

FIGURE 4-12: FIFO DATA COUNTER REGISTER 1 (FDCR1) .....................................................................18

FIGURE 4-13: FIFO DATA COUNTER REGISTER 0 (FDCR0) .....................................................................18

FIGURE 4-14: FIFO THRESHOLD REGISTER 2 (FTHR2)............................................................................19

FIGURE 4-15: FIFO THRESHOLD REGISTER 1 (FTHR1)............................................................................19

FIGURE 4-16: FIFO THRESHOLD REGISTER 0 (FTHR0)............................................................................19

FIGURE 4-17: PORT REGISTER SPACE ......................................................................................................20

FIGURE 4-18: HS-PORT DATA REGISTER 2 ...............................................................................................21

FIGURE 4-19: EXAMPLE OF A 32 BIT PORT DATA REGISTER WRITE ACCESS.....................................22

FIGURE 4-20: HS-PORT DATA REGISTER 1 ...............................................................................................23

FIGURE 4-21: HS-PORT DATA REGISTER 0 ...............................................................................................23

FIGURE 4-22: PORT DATA REGISTER 5 (PDR5).........................................................................................24

FIGURE 4-23: PORT DATA REGISTER 4 (PDR4).........................................................................................24

FIGURE 5-1 : PCI9030 HEADER....................................................................................................................25

FIGURE 5-2 : PCI9030 PCI BASE ADDRESS USAGE ..................................................................................26

FIGURE 5-3 : PCI9030 LOCAL CONFIGURATION REGISTER ....................................................................27

FIGURE 5-4 : CONFIGURATION EEPROM...................................................................................................28

FIGURE 6-1 : LOCAL BUS LITTLE/BIG ENDIAN...........................................................................................30

FIGURE 7-1 : I/O CIRCUITRY ........................................................................................................................32

FIGURE 7-2 : JUMPER POSITIONS FOR GROUND OPTION.......................................................................33

FIGURE 7-3 : JUMPER POSITIONS FOR PORT 2 SIGNAL OPTION ...........................................................33

FIGURE 7-4 : JUMPER POSITIONS FOR BACK I/O OPTIONS.....................................................................34

FIGURE 8-1 : P14 I/O PIN ASSIGNMENT......................................................................................................35

FIGURE 8-2 : FRONT I/O PIN ASSIGNMENT................................................................................................36

Summary of Contents for TPMC682-10

Page 1: ...September 2006 D76682800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany www tews com Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com 9190 Double D...

Page 2: ...S TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or...

Page 3: ...TPMC682 User Manual Issue 1 1 Page 3 of 36 Issue Description Date 1 0 First Issue April 2005 1 1 New address TEWS LLC September 2006...

Page 4: ...0x20 18 4 2 10 FIFO Data Counter Register 1 FDCR1 0x24 18 4 2 11 FIFO Data Counter Register 0 FDCR0 0x28 18 4 2 12 FIFO Threshold Register 2 FTHR2 0x30 19 4 2 13 FIFO Threshold Register 1 FTHR1 0x34 1...

Page 5: ...ATA COUNTER REGISTER 1 FDCR1 18 FIGURE 4 13 FIFO DATA COUNTER REGISTER 0 FDCR0 18 FIGURE 4 14 FIFO THRESHOLD REGISTER 2 FTHR2 19 FIGURE 4 15 FIFO THRESHOLD REGISTER 1 FTHR1 19 FIGURE 4 16 FIFO THRESHO...

Page 6: ...O port has a 512 words deep FIFO All I O lines are protected by bus transceivers and ESD protection devices The PLX PCI9030 PCI target chip is used for the PCI interface An interrupt can be generated...

Page 7: ...16 bit handshake ports Port 0 2 and 2 x 8 bit ports Port 4 5 for handshake signals Number of I O Lines Max output current per line 8mA High level 8mA Low level I O Connector PMC P14 I O 64pin Mezzanin...

Page 8: ...Line 0 H3 Port 4 Line 1 H5 Port 4 Line 2 Handshake Output Signals H2 Port 5 Line 0 H4 Port 5 Line 1 H6 Port 5 Line 2 Input Transfers If input direction is set for a handshake port H1 H3 H5 input sign...

Page 9: ...s The peripheral accepts the data by a falling edge on H1 H3 H5 which causes the next word to be moved to the corresponding output H2 H4 H6 indicates that new data has been moved to the output If H2 H...

Page 10: ...anual Issue 1 1 Page 10 of 36 The typical delay time between a falling edge on H1 H3 H5 and the next falling edge on H2 H4 H6 signaling new valid output data is about 180ns Figure 3 2 Output Transfer...

Page 11: ...by using the PCI9030 local spaces PCI9030 Local Space PCI9030 PCI Base Address Offset in PCI Configuration Space PCI Space Mapping Size Byte Port Width Bit Endian Mode Description 0 2 0x18 MEM 64 32...

Page 12: ...0x12 HANDSHAKE STATUS AND CONTROL REGISTER 1 HSCR1 8 0x13 HANDSHAKE STATUS AND CONTROL REGISTER 0 HSCR0 8 0x14 TIMEOUT COUNTER PRELOAD REGISTER 2 TCPR2 32 0x18 TIMEOUT COUNTER PRELOAD REGISTER 1 TCPR1...

Page 13: ...es of one port have the same direction Bit Symbol Description Access Reset Value 31 8 Reserved 0 for reads 0 7 R 6 HS PORT2_DIR Port 2 Data Direction 0 Port is Input 1 Port is Output R W 00 5 PORT5_DI...

Page 14: ...Status Flag 0 no Timeout Event 1 active Timeout Event R W 0 3 TOUT_EN2 Read Timeout Enable 0 Read Timeout Counter halted 1 Read Timeout Counter enabled R W 0 2 Reserved 0 for reads 0 1 INT_EN2 Port 2...

Page 15: ...UT_EN1 Read Timeout Enable 0 Read Timeout Counter halted 1 Read Timeout Counter enabled R W 0 2 Reserved 0 for reads 0 1 INT_EN1 Port 1 Interrupt Enable 0 Interrupts disabled 1 Interrupts enabled R W...

Page 16: ...UT_EN0 Read Timeout Enable 0 Read Timeout Counter halted 1 Read Timeout Counter enabled R W 0 2 Reserved 0 for reads 0 1 INT_EN0 Port 0 Interrupt Enable 0 Interrupts disabled 1 Interrupts enabled R W...

Page 17: ...gister 1 TCPR1 0x18 Bit Symbol Description Access Reset Value 31 16 Reserved 0 for reads 0 15 0 TOUT_CNTRPREL1 Timeout Value for Read Access multiply value with 33 times the PCI cycle time for resulti...

Page 18: ...ter 2 FDCR2 4 2 10 FIFO Data Counter Register 1 FDCR1 0x24 Bit Symbol Description Access Reset Value 31 10 Reserved 0 for reads 0 9 0 FIFO_CNTR1 Amount of data words in FIFO 1 R 0x000 Figure 4 12 FIFO...

Page 19: ...ster 1 FTHR1 0x34 Bit Symbol Description Access Reset Value 31 10 Reserved 0 for reads 0 9 0 FIFO_FTR1 Threshold of FIFO 1 for setting of FIFO_STATUS1 R W 0x040 Figure 4 15 FIFO Threshold Register 1 F...

Page 20: ...ffset to PCI Base Address 3 Register Name Size Bit Access Width Bit 0x0 or 0x2 HS PORT 2 DATA REGISTER PDR2 16 16 32 0x4 or 0x6 HS PORT 1 DATA REGISTER PDR1 16 16 32 0x8 or 0xA HS PORT 0 DATA REGISTER...

Page 21: ...T_8 7 PORT2_BIT_7 6 PORT2_BIT_6 5 PORT2_BIT_5 4 PORT2_BIT_4 3 PORT2_BIT_3 2 PORT2_BIT_2 1 PORT2_BIT_1 0 PORT2_BIT_0 Port 2 bit 0 15 R W 0 Figure 4 18 HS Port Data Register 2 For performance reasons it...

Page 22: ...TPMC682 User Manual Issue 1 1 Page 22 of 36 Figure 4 19 Example of a 32 Bit Port Data Register Write Access...

Page 23: ...1_BIT_4 3 PORT1_BIT_3 2 PORT1_BIT_2 1 PORT1_BIT_1 0 PORT1_BIT_0 Port 1 bit 0 15 R W 0 Figure 4 20 HS Port Data Register 1 4 3 3 HS Port Data Register 0 PDR0 0x8 or 0xA Bit Symbol Description Access Re...

Page 24: ...ORT5_BIT_1 Handshake output signal H4 R W 0 0 PORT5_BIT_0 Handshake output signal H2 R W 0 Figure 4 22 Port Data Register 5 PDR5 4 3 5 Port Data Register 4 PDR4 0xD Bit Symbol Description Access Reset...

Page 25: ...s 2 for Local Address Space 0 Y FFFFFFC0 0x1C PCI Base Address 3 for Local Address Space 1 Y FFFFFFF0 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Add...

Page 26: ...mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the...

Page 27: ...ange 0x0000_0000 0x10 Local Exp ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000_0001 0x18 Local Re map Register Space 1 0x0000_0041 0x1C Local Re map Register Space 2 0x0000_0000 0x20...

Page 28: ...0x0003 0x0FFF 0xFFC0 0x0FFF 0xFFF0 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x0041 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x1581 0x20A0 0x0540 0x20A0 0x0000 0x...

Page 29: ...Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus L...

Page 30: ...med to operate in Big or Little Endian Mode Big Endian Little Endian 32 Bit 32 Bit Byte 0 D 31 24 Byte 0 D 7 0 Byte 1 D 23 16 Byte 1 D 15 8 Byte 2 D 15 8 Byte 2 D 23 16 Byte 3 D 7 0 Byte 3 D 31 24 16...

Page 31: ...d a value of 0 indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TPMC682 ED Engineering Documentation Use the PCI Base Address 0 Offset or PC...

Page 32: ...ction see figure below I O Circuitry The maximum output current per line is 8mA There are no pull up resistors therefore unused inputs should be tied to Low or High Please note that the length of flat...

Page 33: ...d or port 2 8 15 signals by zero ohm resistors For removing zero ohm resistors work on a grounded static free work surface The pads of the zero ohm resistors allow making a direct solder connection be...

Page 34: ...10 R10 ground default R29 60 Port 2 I O Line 11 R11 ground default R35 61 Port 2 I O Line 12 R7 ground default R31 62 Port 2 I O Line 13 R6 ground default R36 63 Port 2 I O Line 14 R5 ground default...

Page 35: ...t 0 I O Line 14 47 Port 5 I O Line 6 16 Port 0 I O Line 15 48 Port 5 I O Line 7 17 Port 1 I O Line 0 49 Port 2 I O Line 0 18 Port 1 I O Line 1 50 Port 2 I O Line 1 19 Port 1 I O Line 2 51 Port 2 I O L...

Page 36: ...t 5 I O Line 6 14 Port 0 I O Line 13 48 Port 5 I O Line 7 15 Port 0 I O Line 14 49 Port 2 I O Line 0 16 Port 0 I O Line 15 50 Port 2 I O Line 1 17 Port 1 I O Line 0 51 Port 2 I O Line 2 18 Port 1 I O...

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