TPMC682 User Manual Issue 1.1
Page 17 of 36
4.2.6 Timeout Counter Preload Register 2 (TCPR2; 0x14)
Bit
Symbol
Description
Access
Reset
Value
31..16
-
Reserved (0 for reads)
-
0
15..0 TOUT_CNTRPREL2
Timeout Value for Read Access
(multiply value with 33 times the PCI cycle time for
resulting timeout delay time)
R/W 0x00FF
Figure 4-8 : FIFO Threshold Register 2 (FTHR2)
4.2.7 Timeout Counter Preload Register 1 (TCPR1; 0x18)
Bit
Symbol
Description
Access
Reset
Value
31..16
-
Reserved (0 for reads)
-
0
15..0 TOUT_CNTRPREL1
Timeout Value for Read Access
(multiply value with 33 times the PCI cycle time for
resulting timeout delay time)
R/W 0x00FF
Figure 4-9 : FIFO Threshold Register 1 (FTHR1)
4.2.8 Timeout Counter Preload Register 0 (TCPR0; 0x1C)
Bit
Symbol
Description
Access
Reset
Value
31..16
-
Reserved (0 for reads)
-
0
15..0 TOUT_CNTRPREL0
Timeout Value for Read Access
(multiply value with 33 times the PCI cycle time for
resulting timeout delay time)
R/W 0x00FF
Figure 4-10: FIFO Threshold Register 0 (FTHR0)
