TPMC682 User Manual Issue 1.1
Page 4 of 36
Table of Contents
1
PRODUCT DESCRIPTION ......................................................................................... 6
2
TECHNICAL SPECIFICATION................................................................................... 7
3
HANDSHAKE MODE ................................................................................................. 8
4
LOCAL SPACE ADDRESSING................................................................................ 11
4.1
PCI9030 Local Space Configuration ...........................................................................................11
4.2
FPGA Control Register Space .....................................................................................................12
4.2.1
Interrupt and FIFO Control Register (IFCR; 0x00) .............................................................13
4.2.2
Port Data Direction Register (PDDR; 0x04) .......................................................................13
4.2.3
Handshake Status and Control Register 2 (HSCR2; 0x11)................................................14
4.2.4
Handshake Status and Control Register 1 (HSCR1; 0x12)................................................15
4.2.5
Handshake Status and Control Register 0 (HSCR0; 0x13)................................................16
4.2.6
Timeout Counter Preload Register 2 (TCPR2; 0x14).........................................................17
4.2.7
Timeout Counter Preload Register 1 (TCPR1; 0x18).........................................................17
4.2.8
Timeout Counter Preload Register 0 (TCPR0; 0x1C) ........................................................17
4.2.9
FIFO Data Counter Register 2 (FDCR2; 0x20) ..................................................................18
4.2.10
FIFO Data Counter Register 1 (FDCR1; 0x24) ................................................................18
4.2.11
FIFO Data Counter Register 0 (FDCR0; 0x28) ................................................................18
4.2.12
FIFO Threshold Register 2 (FTHR2; 0x30) ......................................................................19
4.2.13
FIFO Threshold Register 1 (FTHR1; 0x34) ......................................................................19
4.2.14
FIFO Threshold Register 0 (FTHR0; 0x38) ......................................................................19
4.3
FPGA Port Register Space ...........................................................................................................20
4.3.1
HS-Port Data Register 2 (PDR2; 0x0 or 0x2).....................................................................21
4.3.2
HS-Port Data Register 1 (PDR1; 0x4 or 0x6).....................................................................23
4.3.3
HS-Port Data Register 0 (PDR0; 0x8 or 0xA) ....................................................................23
4.3.4
Port Data Register 5 (PDR5; 0xC)......................................................................................24
4.3.5
Port Data Register 4 (PDR4; 0xD)......................................................................................24
5
PCI9030 TARGET CHIP ........................................................................................... 25
5.1
PCI Configuration Registers (PCR) .............................................................................................25
5.1.1
PCI9030 Header .................................................................................................................25
5.1.2
PCI Base Address Initialization ..........................................................................................26
5.2
Local Configuration Register (LCR)............................................................................................27
5.3
Configuration EEPROM ................................................................................................................28
5.4
Local Software Reset....................................................................................................................29
6
CONFIGURATION HINTS ........................................................................................ 30
6.1
Big / Little Endian..........................................................................................................................30
7
INSTALLATION........................................................................................................ 32
7.1
I/O Circuit .......................................................................................................................................32
7.2
Back I/O Configuration .................................................................................................................33
8
PIN ASSIGNMENT – I/O CONNECTOR .................................................................. 35
8.1
Back I/O P14 ..................................................................................................................................35
8.2
Front Panel I/O...............................................................................................................................36
