Tews Technologies TPMC682-10, User Manual

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TPMC682 User Manual Issue 1.1 Page 14 of 36
4.2.3 Handshake Status and Control Register 2 (HSCR2; 0x11)
See chapter “Handshake Mode” for a description of the mode and the configuration bits in the
Handshake Status and Control Registers.
Bit Symbol Description Access
Reset
Value
7 FIFO_STATUS2 FIFO Status Flag
0 : FIFO level within threshold of FTHR2
1 : FIFO level exceeds threshold of FTHR2 R 0
6..5 PORT2_HS H6 Handshake Output Protocol
00 : none
10 : Interlocked Handshake Protocol
11 : Pulsed Handshake Protocol R/W 00
4 TOUT_STATUS2 Read Timeout Status Flag
0 : no Timeout Event
1 : active Timeout Event R/W 0
3 TOUT_EN2 Read Timeout Enable
0 : Read Timeout Counter halted
1 : Read Timeout Counter enabled R/W 0
2 - Reserved (‘0’ for reads) - 0
1 INT_EN2 Port 2 Interrupt Enable
0 : Interrupts disabled
1 : Interrupts enabled R/W 0
0 - Reserved (‘1’ for reads) - 1
Figure 4-5 : Handshake Status and Control Register 2 (HSCR2)
The Handshake Status and Control Register 2 controls 16 bit Handshake Port 2.
After the Timeout Counter is enabled, it is started with the first falling edge on H5.
When interrupts are enabled globally (bit 0 of IFCR is ‘1’) and for Port 2 (bit 1 is ‘1’), an interrupt
is generated when Timeout Status Flag is ‘1’ or FIFO Status Flag is ‘1’.
The Timeout Status Flag is acknowledged by writing ‘1’ to bit 4.