TPMC682 User Manual Issue 1.1
Page 21 of 36
4.3.1 HS-Port Data Register 2 (PDR2; 0x0 or 0x2)
Bit
Symbol
Description
Access
Reset
Value
15 PORT2_BIT_15
14 PORT2_BIT_14
13 PORT2_BIT_13
12 PORT2_BIT_12
11 PORT2_BIT_11
10 PORT2_BIT_10
9 PORT2_BIT_9
8 PORT2_BIT_8
7 PORT2_BIT_7
6 PORT2_BIT_6
5 PORT2_BIT_5
4 PORT2_BIT_4
3 PORT2_BIT_3
2 PORT2_BIT_2
1 PORT2_BIT_1
0 PORT2_BIT_0
Port 2 bit 0-15
R/W
0
Figure 4-18: HS-Port Data Register 2
For performance reasons it might be useful to read/write 32 bit lwords at once over the PCI bus
to the FIFOs. They will be split into two 16 bit word accesses after another; the word with the
lower address will be read/written at first to/from the FIFO (see example in next figure).
