TPMC682 User Manual Issue 1.1
Page 8 of 36
3 Handshake Mode
There are three 16 bit ports available (Port 0 - 2), input and output transfers are buffered by FIFOs,
each 512 words deep. Buffering allows orderly transfers by using the handshake pins in one of two
programmable protocols.
Use of buffering is most beneficial in situations where a peripheral device and the computer system
are capable of transferring data at roughly the same speed. Buffering allows the write operation of the
data transmitter to be overlapped with the fetch operation of the data receiving device. Thus,
throughput may be greatly enhanced. If there is a large mismatch in transfer capability between the
computer and the peripheral, little or no benefit is obtained. In these cases there is no penalty in using
buffering.
Port 4 is an input port, bit 0, 1 and 2 of port 4 are used as handshake input signals H1/H3/H5.
Port 5 is an output port, bit 0, 1 and 2 are the handshake output signals H2/H4/H6. The action is
programmable.
The FIFO_STATUS0/1/2 flag, which is bit 7 of the Handshake Status and Control Registers
HSCR0/1/2, gives information about the fill status of the FIFO. An interrupt is triggered if
FIFO_STATUS0/1/2 flag is set and it is enabled by bit 1 of Handshake Status and Control Register
HSCR0/1/2 as well as the global interrupt is enabled: bit 0 of IFCR.
H1 and H2 belong to the 16 bit port on port 0, H3/H4 belong to port 1 and H5/H6 belong to port 2.
Handshake Input
Signals
H1: Port 4 Line 0
H3: Port 4 Line 1
H5: Port 4 Line 2
Handshake Output
Signals
H2: Port 5 Line 0
H4: Port 5 Line 1
H6: Port 5 Line 2
Input Transfers:
If input direction is set for a handshake port, H1 (H3/H5) input signal is used for acquisition of data.
Data is buffered on a falling edge of H1 (H3/H5). FIFO_STATUS0/1/2 is set when the number of
stored data words in the FIFO exceeds the value specified by the corresponding FIFO threshold
register FTHR0/1/2. If the handshake output signals H2 (H4/H6) are used, they indicate whether there
is room for more data in the FIFO or not.
If H2 (H4/H6) output is used, it may be in the interlocked or pulsed input handshake protocol. The
protocol is set by bit 5 and 6 of the Handshake Status and Control Registers HSCR0/1/2.
In the interlocked input handshake protocol signal H2 (H4/H6) is cleared when the port input buffers
are ready to accept new data. It is set following the falling edge of the H1 (H3/H5) input. When ready
for new data, H2 (H4/H6) is cleared again. When FIFO is full H2 (H4/H6) remains high until data is
removed by a read of port data register. Thus, anytime H2 (H4/H6) output is low, new input data may
be entered by a falling edge on H1 (H3/H5). At other times transitions of H1 (H3/H5) are ignored.
In the pulsed input handshake protocol signal H2 (H4/H6) is cleared in the same way as in the
interlocked input protocol, but never remains low longer than four clock cycles. Typically a four-clock
cycle pulse is generated. But in the case that a subsequent H1 (H3/H5) falling edge occurs before
termination of the pulse, H2 (H4/H6) is set immediately high. Thus, anytime after a falling edge of the
H2 (H4/H6) pulse, new data may be entered in the buffers.
