DE10-Agilex
User Manual
77
www.terasic.com
January 29,
2021
Chapter 4
CFI-Flash Programming
n this chapter, we will introduce how to use the AVSTx16 configuration method to
load their design file from the flash memory device to the FPGA after the board
power on. As shown in
, the System MAX 10 FPGA is the core
component of this configuration system. A Parallel Flash Loader II (PFL II) IP is
implemented in the System MAX 10 FPGA, allowing users to send bit stream files of
user
’s project form host to the System MAX 10 FPGA through the JTAG interface.
Then, the bit stream files will be written into the CFI Flash connected to the System
MAX 10 FPGA via the PFL II IP.
After the user
’s bit stream files are stored into the CFI Flash device, when the
DE10-Agilex board is powered on, the PFL II IP in the System MAX 10 FPGA will
automatically load the bit stream file from the CFI Flash first, and then configure the
FPGA through the Avalon-ST x16 interface.
In this chapter, we will introduce how to correctly set the FPGA to work in AVSTx16
mode, how to program bit stream files into the CFI Flash, and how to switch the image
file to be loaded.
I
