Terasic DE10-Agiles, User Manual

Page: 24 / 208

DE10-Agilex
User Manual 24 www.terasic.com
January 29,
2021
Table 2-5 Push-button Pin Assignments, Schematic Signal Names, and
Functions
Board
Reference
Schematic
Signal
Name
Description
I/O
Standard
Agilex
Pin Number
PB0 BUTTON0 High Logic Level when the button
is not pressed
1.2V PIN_J54
PB1 BUTTON1 1.2V PIN_G54
There is also a reset button on the board connected to the Agilex FPGA and System
MAX FPGA at the same time, allowing users to reset the logic in Agilex FPGA and
System MAX 10 FPGA.
Table 2-6 CPU Reset Button Pin Assignments, Schematic Signal Names, and
Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Agilex
Pin Number
PB3 CPU_RESET_n
High Logic Level when the
button is not pressed
1.2V PIN_G56

User-Defined Dip Switch
There are two positions dip switches (SW0 and SW1) on the FPGA board to provide
additional FPGA input control. When a position of dip switch is in the DOWN position or
the UPPER position, it provides a low logic level or a high logic level to the Agilex
FPGA, respectively.
Table 2-7 lists the signal names and their corresponding Agilex device pin numbers.
Table 2-7 Dip Switch Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Agilex
Pin Number
SW0 SW0 High logic level when SW in the
UPPER position.
1.2V PIN_H51
SW1 SW1 1.2V PIN_F51