DE10-Agilex
User Manual
108
www.terasic.com
January 29,
2021
Chapter 6
Memory Reference
Design
he FPGA development board includes four DDR4 SODIMM Sockets. This
chapter will show three examples which use the memory controller
Agilex
External Memory Interfaces (Agilex EMIF)
to perform memory test functions.
The source codes of these examples are all available on the FPGA System CD. These
three examples are:
DDR4 SDRAM Test: Test four DDR4-2666 8GB ECC SODIMM Module.
DDR4 SDRAM Test by Nios II: Test four
DDR4-2666 8GB ECC SODIMM
Module with Nios II program.
6.1
DDR4 SDRAM Test
This demonstration performs a memory test function on the four DDR4-2666 ECC
SO-DIMM on the DE10-Agilex. The memory size of each DDR4 SDRAM SO-DIMM
used in this test is 8 GB.
Function Block Diagram
shows the function block diagram of this demonstration. There are four
DDR4 SDRAM controllers. The controller uses 166.667 MHz as a reference clock. It
generates one 1333MHz clock as memory clock from the FPGA to the memory and the
controller itself runs at quarter-rate in the FPGA i.e. 166.667 MHz.
T
