DE10-Agilex
User Manual
67
www.terasic.com
January 29,
2021
3.2
General Design Flow
This section will introduce the general design flow to build a project for the FPGA board
via the System Builder. The general design flow is illustrated in
Users should launch System Builder and create a new project according to their design
requirements. When users complete the settings, the System Builder will generate two
major files which include top-level design file (.v) and the Quartus Prime setting file
(.qsf).
The top-level design file contains top-level Verilog wrapper for users to add their own
design/logic. The Quartus Prime setting file contains information such as FPGA device
type, top-level pin assignment, and I/O standard for each user-defined I/O pin.
Finally, the Quartus Prime programmer must be used to download SOF file to the
FPGA board using JTAG interface.
Figure 3-1 the general design flow of building a project
