DE10-Agilex
User Manual
55
www.terasic.com
January 29,
2021
of channel 3
Differential I/O
QSFPDDA_RX_n3
Receiver inverted data of
channel 3
High Speed
Differential I/O
PIN_BM11
QSFPDDA_RX_p4
Receiver non-inverted data
of channel 4
High Speed
Differential I/O
PIN_BP7
QSFPDDA_RX_n4
Receiver inverted data of
channel 4
High Speed
Differential I/O
PIN_BN8
QSFPDDA_RX_p5
Receiver non-inverted data
of channel 5
High Speed
Differential I/O
PIN_BV7
QSFPDDA_RX_n5
Receiver inverted data of
channel 5
High Speed
Differential I/O
PIN_BU8
QSFPDDA_RX_p6
Receiver non-inverted data
of channel 6
High Speed
Differential I/O
PIN_BR10
QSFPDDA_RX_n6
Receiver inverted data of
channel 6
High Speed
Differential I/O
PIN_BT11
QSFPDDA_RX_p7
Receiver non-inverted data
of channel 7
High Speed
Differential I/O
PIN_BW10
QSFPDDA_RX_n7
Receiver inverted data of
channel 7
High Speed
Differential I/O
PIN_BY11
QSFPDDA_REFCLK_p
QSFP-DD port A
transceiver reference clock
p
LVDS
PIN_AJ12
QSFPDDA_REFCLK_n
QSFP-DD port transceiver
reference clock n
LVDS
PIN_AH11
QSFPDDA_INITMODE
Initialization mode
1.2V
PIN_DB21
QSFPDDA_INTERRUPT_n
Interrupt
1.2V
PIN_CV25
QSFPDDA_MOD_PRS_n
Module Present
1.2V
PIN_CR26
QSFPDDA_MOD_SEL_n
Module Select
1.2V
PIN_DB19
QSFPDDA_RST_n
Module Reset
1.2V
PIN_DA20
QSFPDDA_SCL
2-wire serial interface clock
1.2V
PIN_H21
QSFPDDA_SDA
2-wire serial interface data
1.2V
PIN_H23
