Teledyne SP Devices ADQ3 Series, User Manual

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Classification Revision
Public B
Document ID Print date
20-2507 2022-03-31
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Important
The two 1-bit signals record start and record stop may not be asserted in the same data clock cycle.
Thus, the minimum record length is two data clock cycles.
The two index signals define the start and stop positions within the parallel data word. Both indexes are
inclusive. A record starts at the sample indicated by record start index and stops at the sample indicated
by record stop index .
The record start and stop signal must be sent on a clock cycle where the valid signal is asserted
to have any effect. Any custom user logic should always check that the valid signal is asserted before
reacting to the record start signal. Note that record start and record stop signals may be asserted for
multiple cycles as long as one—and only one—clock cycle is overlapping with the valid signal. Fig. 5
presents a timing diagram where the valid signal is always asserted. In Fig. 6 , data is reduced by the
user logic module. Note that the is no requirement for the valid signal to be periodic, it may be asserted
and deasserted as needed.
Clock
Valid
Record start
Record start index 0
Record stop
Record stop index 7
data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
timestamp T0
Figure 5: Timing diagram for the record framing signals when no data reduction is active. The record
spans ten data clock cycles.
Clock
Valid
Record start
Record start index 0
Record stop
Record stop index 7
Data D0 D1 D2 D3 D4 D5 D6
Timestamp T0
Figure 6: Timing diagram for the record framing signals with data reduction active. The record spans
five valid data clock cycles durring thirteen clock cycles.
It is important that the integrity of the record bits is preserved. The second user logic area must output
one—and only one—record stop event for each record start event. To discard a record, record start and
record stop assertions must be removed in pairs . If multiple record start events are output without their
corresponding record stop events, data corruption will ensue. Note that it is valid to create an infinite
stream of data by generating a single record start event. Listed below is a summary of the properties of
the record bits.
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