Classification
Revision
Public
B
Document ID
Print date
20-2507
2022-03-31
serve as a way to remove modules in the base design to free up FPGA resources, provided that the
application does not require the features they provide. For example, the parameter
REMOVE_FILTER
removes the built-in FIR filter if set to a nonzero value. This frees up DSP and routing resources in the
FPGA fabric.
3.4
Building the Design
To build the entire design, execute the command
devkit_build
in the Tcl console. Depending on the computer specifications and the complexity of the design as a whole,
i.e. the precomplied design and the user logic together, this may take several hours. Once the process
is complete, an
.mcs
file has been generated in the
artifacts/latest/
directory. This file represents
a new firmware for the digitizer and may be uploaded using the
ADQUpdater
application. Refer to the
ADQUpdater user guide [
] for instructions on how to manage the digitizer’s firmware.
3.5
Working with the Design
This section describes the workflow of adding customized logic functions to the digitizer firmware.
3.5.1
Typical Design Flow
This section outlines the typical design flow for the development kit.
1.
Set up the development kit project as described in Section
2.
Modify or insert new Verilog code into
user_logic1.v
or
user_logic2.v
. This operation can be
broken down into four steps:
(a)
Extract
data
,
data valid
and other relevant bus signals using the
bus extraction macros
(see
Section
(b)
Process the extracted signals, i.e. stimulate the custom user design.
(c)
Insert the processed data, data valid and relevant bus signals using the
bus insertion macros
(see Section
(d)
Set the correct value for the
BUS_PIPELINE
delay parameter to keep the correct time relation
between signals that were not manually inserted.
3.
Generate the FPGA configuration file (
.mcs
file) by using one of the two methods outlined below:
•
Automatic
(a)
Execute the command
devkit_build
in the Tcl console.
•
Manual
ADQ3 Series FWDAQ Development Kit
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