Classification
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Public
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20-2507
2022-03-31
5
Data Bus Signals
This section provides a reference for the bus signals that are present on the data buses. Each section
defines a bus segment (which may consist of one or several signals) and provides a description of
its functionality and purpose. The interface functions are named starting with one of the two prefixes
insert_*
or
extract_*
, to separate insertion and extraction. The functions are then further split into
common_*
and
channel_*
.
Common
signals are shared between all channels, with only a single entry
on the bus, while the
channel
signals have one entry for each data channel. The functions to interface
with the latter signal type take an additional argument to identify the target channel. Table
lists the
documented bus signals and should be used as an index to navigate this section.
Example
To extract the common timestamp from the type 1 data bus (first user logic area), use
extract_common_timestamp(DONT_CARE)
where
DONT_CARE
can be any integer in practice since the argument is not used. For data bus type 2
(second user logic area), each channel has its own timestamp. For example,
extract_channel_timestamp(0)
extracts the timestamp from channel A and
extract_channel_timestamp(1)
from channel B and so on.
Example
To insert the common timestamp from the type 1 data bus (first user logic area), use
insert_common_timestamp(timestamp)
where
timestamp
is the 64-bit wide signal to insert. For data bus type 2 (second user logic area), each
channel has its own timestamp. For example,
insert_channel_timestamp(timestamp, 0)
inserts the timestamp to channel A and
insert_channel_timestamp(timestamp, 1)
to channel B and so on.
Important
Bus signals not mentioned in this section are not yet implemented. Do not interact with these signals
from the development kit.
ADQ3 Series FWDAQ Development Kit
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