Teledyne SP Devices ADQ3 Series, User Manual

Page: 19 / 40

Classification Revision
Public B
Document ID Print date
20-2507 2022-03-31
4.4 AXI Control Bus
Each user logic area can be accessed via the AXI control bus which provides a connection between
the custom logic and the software running on the host computer. A transaction cannot be started from
a user logic area and thus, communicating between the two modules using the control bus is not sup-
ported. Instead, transactions are initiated by the host interface which in turn is initiated from the ADQAPI,
specifically by using the functions to read or write user registers:
•
ReadUserRegister()
•
WriteUserRegister()
Refer to the ADQ3 series user guide [ 3 ] for the API documentation.

Note
Transactions on the control bus cannot be initiated from the user design, only from calling specific
functions in the ADQAPI.
4.4.1 Control Bus Signals
The control bus interface follows the AXI4-Lite format. The user logic needs to implement an AXI4-Lite
slave instance.
4.5 Data Bus
The stream of ADC data, its associated control signals and other metadata all propagate on the data
bus. The various signals are intricately related to each other and it is crucial that their relation in time is
kept intact while they are processed by the custom logic.

Important
The bus signals are closely related to each other and it is crucial that their relation in time is kept intact
through the user logic areas.
The development kit includes predefined functions to simplify the bus operations. There are two points
where the user design interfaces with the data bus: extraction and insertion . As the names suggest,
targeted signals are extracted from the bus and input to the custom logic to create a response. The
logic’s output signals are inserted back into the data bus and continues to propagate through the design
(see Fig. 3 ). Signals that are not inserted back into the data bus will be subjected to pipelining with a
delay equal to the value of the
BUS_PIPELINE
parameter. This parameter must be defined in the same
HDL source file as the bus operations. Fig. 4 outlines the principle of working with the bus signals in the
user space.
4.5.1 Two Bus Definitions
The design has two different data bus definitions that are labeled data bus type 1 (DBT1) and data
bustype 2 (DBT2). The first user logic area uses the DBT1 bus definition while the second user logic
area uses the DBT2 definition. The two bus definitions each have their own set of functions to support
ADQ3 Series FWDAQ Development Kit spdevices.com Page 18 of 38