Teledyne SP Devices ADQ3 Series, User Manual

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Classification Revision
Public B
Document ID Print date
20-2507 2022-03-31
Table 3: An overview of the data bus signals, including for which bus types the signals are present, and
whether they are shared between the channels or separate.
Signal Page DBT1 DBT2
Timestamp 21 Common Per channel
Timestamp synchronization 21 Common Per channel
Trigger 22 Per channel Per channel
Overrange indicator 23 Per channel Per channel
General purpose 23 Per channel Per channel
ADC sample data 23 Per channel Per channel
Valid 23 N/A Per channel
Record 23 N/A Per channel
User ID 25 N/A Per channel
5.1 Timestamp
The timestamp signal provides a monotonically increasing counter to serve as a time base for the digitizer.
The signal is 64 bits wide and holds an unsigned value that may be synchronized to external and internal
events by using the timestamp synchronization mechanism. The timestamp value during a data clock
cycle where record start is asserted propagates to the user space in the host computer via the record
header. The timestamp is shared between all channels for data bus type 1 and per channel for type 2.
5.2 Timestamp Synchronization
The timestamp synchronization bus segment is shared between all channels for data bus type 1 and
per channel for type 2, just like the timestamp . The segment consists of three signals, described in the
following sections.
5.2.1 Sample Index
The sample index is an unsigned value representing the integer part of the position of the timestamp
synchronization event within the parallel sample data in a clock cycle. There is no fractional part, like in
the trigger segment, so the value always indicates the index of the closest sample earlier in time. For
example, if an event source with subsample precision is used to synchronize the timestamp, the position
‘3.6’ would propagate as ‘3’.
5.2.2 Count
The counter is tasked with keeping track of the number of timestamp synchronization events since the
mechanism was last armed and is represented by an unsigned number. The counter value during a data
clock cycle where record start is asserted propagates to the user’s application via the record header—
provided the mechanism is set up and activated.
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