Teledyne SP Devices ADQ3 Series, User Manual

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Classification Revision
Public B
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20-2507 2022-03-31
5.4 Overrange
The overrange indicator is a 1-bit signal indicating that at least one sample within the parallel sample
data in this clock cycle has saturated to the minimum or maximum value of the dynamic range.
5.5 General Purpose
The general purpose signal is 16 bits wide and may be used to achieve various firmware-specific goals.
The default data acquisition firmware does not impose any restrictions on the signal, but special-purpose
firmwares may reserve the signal for internal use. If no functional conflict exists, the signal may be used
to, e.g. pass information between the two user logic areas in a well-defined manner. However, if the
sample skip mechanism is active, only information passed while record start is asserted is preserved
throughout the data path. Additionally, the value during a data clock cycle which asserts the record start
bit, will propagate to the user space in the host computer via the record header.
5.6 Sample Data
The sample data signal holds the samples of the analog inputs on a per-channel basis and consists of
several samples in parallel, as explained in Section 4.1 . The width of the signal depends on the firmware
configuration and target device. For this purpose, each user logic area defines constants which must
be used to parametrize a custom design. For example, UL1 defines the width of one sample as
DBT1_-
CHANNEL0_BITS_PER_SAMPLE
and the number of parallel samples as
DBT1_CHANNEL0_PARALLEL_SAMPLES
for channel A. A sample is encoded using the 2’s complement representation. The data is MSB aligned,
meaning that the MSB of the raw ADC data is located at bit index
DBT1_CHANNEL0_BITS_PER_SAMPLE-1
for channel A.
5.7 Valid
The valid signal exists on a per-channel basis on the type 2 data bus. The signal is one bit wide and when
asserted, every sample within the parallel sample data in the current clock cycle is considered valid. For
the type 1 data bus, the signal is not present since by definition, every clock cycle is considered valid.
5.8 Record
The record bus segment is only present on the type 2 data bus and consists of the signals that frame a
record. The following section describe the individual signals.
5.8.1 Start, Start Index, Stop and Stop Index
The two 1-bit signals record start and record stop work together frame a record of sample data. They
are inclusive , meaning that if either signal is asserted, the sample data associated with that data clock
cycle belongs to the record. The signals may not be asserted in the same data clock cycle.
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