Classification
Revision
Public
B
Document ID
Print date
20-2507
2022-03-31
User logic 1
This user logic area is intended to be used to process the incoming samples before any data
reduction has been applied. Refer to Section
for a more detailed description of the module.
FIR filter
The base design contains a FIR filter module able to subject the data from each channel to a
digital filter function. The FPGA resources used by this module can be reclaimed by the user.
See Section
for more information.
Sample skip
The sampling rate can be reduced by the sample skip module. For example, setting the sample
skip factor to 4 means that every fourth sample is kept and the others are discarded.
Level trigger
This module is used to insert events on the data bus based on the signal level within the data bus
channels.
Acquisition
The acquisition module is tasked with framing the channels on the data bus into
records
based
on a
trigger event
. The starting point and stopping point of the record is marked by a logic-high
pulse on the
and
data bus signals, respectively.
Barrel shifter
This module rearranges the parallel samples on the bus so that the first entry is the first sample
in the record.
User logic 2
This user logic area is intended for processing data after the record framing and any data reduction
has occurred. Refer to Section
for a more detailed description of the module.
Peer-to-peer packer
The peer-to-peer packer is tasked with converting the information on the data bus into packets
that is suitable for the intended
endpoint
and application.
DRAM FIFO
Before the packets are dispatched to their endpoint, they pass through the on-board DRAM. This
allows the digitizer to buffer packets in the event of a temporary stall on the physical interface or
a short period where the acquisition rate is higher than the readout rate.
DMA
The DMA engine transports packets from the DRAM to a receiving endpoint.
4.3
Clock Domain Crossing Synchronization
A clock domain crossing, CDC, is a boundary where digital signals pass from one clock domain to another.
This boundary constitutes a critical point in the design and care must be taken to
synchronize
signals
ADQ3 Series FWDAQ Development Kit
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