Tektronix 1710J Series, Instruction Manual

Page: 84 / 252

Theory of Operation
5–6
1710J-Series Waveform Monitors
During sync time, the clamp circuit maintains the output of the first amplifier
stage at about +5 V, which is fed back to the clamp circuit, through CR990, to
maintain the proper level.
During non-sync times (active video), CR988 and CR989 are both on to shunt
U892C and greatly reduce the gain. Shunting the active video limits the
saturation of U892C, which allows it to respond quickly to the next sync
transition.
An inverting amplifier, U892B, is the second amplifier stage. It provides
negative-going sync and cleans up any remaining noise or active video on the
signal. Output of the second stage is also fed to the clamp.
The clamp circuit is formed around U892E and U892A. U892E and CR990 form
a current switch. When the first stage output level is at sync tip, current flows
through U892E, which charges C887. At the same time U892B pulls down on
CR887 to provide a discharge path for C887. The result of these opposing
actions is to establish an equilibrium voltage on C887. At the end of sync time
U892C saturates and pulls down on CR990 to shut off U892E.
The three filters are driven from current source Q791 through one of the analog
switch sections of U786. Only one switch section will be closed at a time, as
dictated by its enable, from the microprocessor (Diagram 5) going low.
chrominance filters are clamped to ground when low pass filtering or flat is
selected. In this condition Q777 and Q776 are turned on clamping the chromi-
nance filter outputs to ground.
When the chrominance filter is turned on an additional bias current for the ac-
coupled filters (3.58 and 4.43 MHz) is required. It is supplied by pulling the
emitters of either CR671 or CR670 low with the microprocessor-generated
enable signal, which turns on Q775 to saturate Q774. When Q774 saturates its
collector goes to +11.8 V. Signal current from the enabled filter drives the
emitter of a common base amplifier input to the gain cell (Diagram 2). At a
0 VDC level 2 mA of bias current is added to 1 mA of signal current that drives
the input of the Gain Cell.
When dual filter or dual input display is selected a blanking signal is required to
mask any potential switching transit that might occur. Whenever CH B or FLAT
goes active an RC circuit consisting of C94 (CH B) or C871 (FLAT) and R878
and R885 generates a pulse through Q764. Q765 inverts the blanking pulse,
which is input to the blanking circuitry on Diagram 4.
The calibrator is a common base amplifier, Q587, that is driven by a 100 kHz
square wave from the microprocessor (Diagram 5). It is switched at the 100 kHz
rate. The gain is set by adjusting R689, the Cal Amp. The emitter current drives
the low pass filter (which is at least 30 dB down at 3.58 to 4.43 MHz) through an
analog switch, U585C, which is activated by the microprocessor-generated CAL.
Filter Selection
Calibrator