
Chapter 2 TL1 Reference
Set Phase Zero
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SSU-2000e Technical Reference
12713140-003-2 Revision E.01 – January 2007
Set Phase Zero
This command sets the input phase to zero for the designated port(s) or all input
ports with an aid of null or ALL. If
clksrc
is specified [CLK-A | CLK-B], only the one
phase value is set to zero; otherwise both values are set to zero.
Syntax
SET-PHASE-ZERO:[tid]:[aid]:ctag[::clksrc];
Related Commands
Parameter
Format
Description
aid
S1Ay[-z]
Sets the input phase on the selected Input module or port
to zero
clksrc
CLK-A |
CLK-B
Sets the phase value for the specified Clock module to
zero. If not specified, phase values for both Clock
modules are set to zero.