Supero X9DRL-7F, User Manual

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X9DRL-7F/X9DRL-EF Motherboard User’s Manual
JCOM2
JSD1
P1-DIMMD1
P2-DIMME1
P1-DIMMB1
P2-DIMMH1
P2-DIMMG1
P1-DIMMC1
P2-DIMMF1
COM1
JPW4
JTPM1
LAN2 LAN1
JPW1
JPW2
USB4
JPI2C1
JIPMB1
FAN5
FAN2
FAN3
FAN4
FANA
JPL1 JPL2
JVRM_I2C1 JVRM_I2C2
JPG1
JPS1
JWD1
JLED1
JMLED1
LEDS1
LEDM1
LED1C
LED2
JF1
T-SGPIO1
T-SGPIO2
6-SGPIO2
I-S
AT
A1
I-SATA0
L-SAS0
Battery
JL1
JPS2 JPS3
JOH1 JI2C1 JI2C2
SP1
JUIDB1
USB0/1
X9DRL-7F/EF
Rev.1.01
PCH SLOT3 PCI-E 2.0 X4 (IN X8)
CPU1 SLOT6 PCI-E 3.0 X8
CPU1
VGA
USB8/9
USB6/7
IPMI_LAN
CPU2
JPB1
6-SGPIO1
PCH SLOT2 PCI-E 2.0 X1
CPU1 SLOT4 PCI-E 3.0 X8
I-SATA2
I-SATA3
I-SATA4
P1-DIMMA1
FP CTRL
Intel PCH
LSI 2208
CTRL
BMC
JBT1
LAN
CTRL
LAN
CTRL
L-SAS7
I-SATA5
L-SAS6
L-SAS5
L-SAS4
JPME1
JBR1
BIOS
JSTBY1
L-SAS1
L-SAS2
L-SAS3
JPME2
FAN1
A
B
A. T-SGPIO1
B. T-SGPIO2
C. 6-SGPIO0 (X9DRL-7F)
D. 6-SGPIO1 (X9DRL-7F)
T-SGPIO/6-SGPIO Headers
Four SGPIO (Serial Link General
Purpose Input/Output) headers are
located on the motherboard. T-SGPIO
1/2 support onboard SATA connec-
tions on the motherboard. 6-SGPIO
1/2 support L-SAS connections on the
X9DRL-7F. See the table on the right
for pin definitions.
Note: NC= No Connection
T-SGPIO/6-SGPIO Headers
Pin Definitions
Pin# Definition Pin Definition
1 NC 2 NC
3 Ground 4 Data
5 Load 6 Ground
7 Clock 8 NC
C
D
E
Standby Power Header
The +5V Standby Power header is
located at JSTBY1 on the mother-
board. See the table on the right for
pin definitions. (You must also have a
card with a Standby Power connector
and a cable to use this feature.)
Standby PWR
Pin Definitions
Pin# Definition
1 +5V Standby
2 Ground
3 Wake-up