Supero X9DRL-7F, User Manual

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Chapter 1: Overview
1-5
X9DRL-7F/X9DRL-EF Jumpers
Jumper
Description Default Setting
JBT1
Clear CMOS See Chapter 3
JI
2
C1/JI
2
C2
SMB to PCI-E Slots Off (Disabled)
JPB1 BMC Enable Pins 1-2 (Enabled)
JPG1 VGA Enable Pins 1-2 (Enabled)
JPL1/JPL2 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)
JPS1 L-SAS Enable (X9DRL-7F Only) Pins 1-2 (Enabled)
JWD1 Watch Dog Timer Enable Pins 1-2 (Reset)
X9DRL-7F/X9DRL-EF Connectors
Connectors Description
Battery Onboard Battery (See Chpt. 3 for Used Battery Disposal)
COM1/COM2 Backplane COM Port1/Front Accessible COM2 Header
Fan1-5, FanA CPU/System Fan Headers
JF1 Front Panel Control Header
JIPMB1 4-pin External BMC I
2
C Header (for an IPMI Card)
JL1 Chassis Intrusion
JOH1 Overheat LED Indicator
JPI
2
C1 Power Supply SMBbus I
2
C Header
JPW1/2 12V 8-Pin Power Connectors (See Warning on Pg. 1-6.)
JPW4 24-Pin ATX Main Power Connector (See Warning on Pg. 1-6.)
JSD1 SATA DOM (Device on Module) Power Connector
JSTBY1 5V Standby Power
JTPM1 TPM (Trusted Platform Module)/Port 80
JUIDB UID (Unit Identification) Switch
LAN1/LAN2 G-bit Ethernet Ports 1/2
(IPMI) LAN IPMI_Dedicated LAN
(I-)SATA 0-5 Intel PCH SATA Connectors (0-5)
(L-)SAS 0-7 L-SAS Connectors 0-7 supported by the LSI 2208 controller
(for X9DRL-7F)
(PCH) Slot2 PCI-Express 2.0 x1 Slot from Intel PCH
(PCH) Slot3 PCI-Express 2.0 x4 in x8 Slot from Intel PCH
(CPU1) Slot4 PCI-Express 3.0 x8 Slot from CPU1
(CPU1)Slot6 PCI-Express 3.0 x8 Slot from CPU1
(6-) SGPIO 1/2 Seria_Link General Purpose I/O Headers 0/1 for L-SAS ports
(for X9DRL-7F only)